Merge remote branch 'nouveau/for-airlied' of ../drm-nouveau-next into drm-core-next

* 'nouveau/for-airlied' of ../drm-nouveau-next: (77 commits)
  drm/nouveau: set TASK_(UN)INTERRUPTIBLE before schedule_timeout()
  drm/nv50: fix some not-error error messages
  drm/nouveau: introduce gpio engine
  drm/nv50: correct wait condition for instmem flush
  drm/nouveau: Fix TV-out detection on unposted cards lacking a usable DCB table.
  drm/nouveau: Get rid of the remaining VGA CRTC locking.
  drm/nouveau: Move display init to a new nouveau_engine.
  drm/nouveau: Put back the old 2-messages I2C slave test.
  drm/nouveau: Reset AGP before running the init scripts.
  drm/nv30: Init the PFB+0x3xx memory timing regs.
  drm/nouveau: disable hotplug detect around DP link training
  drm/nv50: add function to control GPIO IRQ reporting
  drm/nouveau: add nv_mask register accessor
  drm/nouveau: fix build without CONFIG_ACPI
  drm/nouveau: Reset CRTC owner to 0 before BIOS init.
  drm/nouveau: No need to lock/unlock the VGA CRTC regs all the time.
  drm/nouveau: Remove useless CRTC_OWNER logging.
  drm/nouveau: Add some generic I2C gadget detection code.
  drm/i2c/ch7006: Don't assume that the specified config points to static memory.
  drm/nv04-nv3x: Implement init-compute-mem.
  ...

Conflicts:
	drivers/gpu/drm/nouveau/nouveau_bios.c

1 files changed, 21 insertions, 37 deletions

diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c
index 65b13b54c5ae..fd7d2b501316 100644
--- a/drivers/gpu/drm/nouveau/nv40_graph.c
+++ b/drivers/gpu/drm/nouveau/nv40_graph.c
@@ -58,6 +58,7 @@ nv40_graph_create_context(struct nouveau_channel *chan)
         struct drm_device *dev = chan->dev;
         struct drm_nouveau_private *dev_priv = dev->dev_private;
         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
+        struct nouveau_grctx ctx = {};
         int ret;
 
         ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size,
@@ -67,20 +68,13 @@ nv40_graph_create_context(struct nouveau_channel *chan)
                 return ret;
 
         /* Initialise default context values */
-        dev_priv->engine.instmem.prepare_access(dev, true);
-        if (!pgraph->ctxprog) {
-                struct nouveau_grctx ctx = {};
-
-                ctx.dev = chan->dev;
-                ctx.mode = NOUVEAU_GRCTX_VALS;
-                ctx.data = chan->ramin_grctx->gpuobj;
-                nv40_grctx_init(&ctx);
-        } else {
-                nouveau_grctx_vals_load(dev, chan->ramin_grctx->gpuobj);
-        }
+        ctx.dev = chan->dev;
+        ctx.mode = NOUVEAU_GRCTX_VALS;
+        ctx.data = chan->ramin_grctx->gpuobj;
+        nv40_grctx_init(&ctx);
+
         nv_wo32(dev, chan->ramin_grctx->gpuobj, 0,
                      chan->ramin_grctx->gpuobj->im_pramin->start);
-        dev_priv->engine.instmem.finish_access(dev);
         return 0;
 }
 
@@ -238,7 +232,8 @@ nv40_graph_init(struct drm_device *dev)
         struct drm_nouveau_private *dev_priv =
                 (struct drm_nouveau_private *)dev->dev_private;
         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
-        uint32_t vramsz;
+        struct nouveau_grctx ctx = {};
+        uint32_t vramsz, *cp;
         int i, j;
 
         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
@@ -246,32 +241,22 @@ nv40_graph_init(struct drm_device *dev)
         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
                          NV_PMC_ENABLE_PGRAPH);
 
-        if (nouveau_ctxfw) {
-                nouveau_grctx_prog_load(dev);
-                dev_priv->engine.graph.grctx_size = 175 * 1024;
-        }
+        cp = kmalloc(sizeof(*cp) * 256, GFP_KERNEL);
+        if (!cp)
+                return -ENOMEM;
 
-        if (!dev_priv->engine.graph.ctxprog) {
-                struct nouveau_grctx ctx = {};
-                uint32_t *cp;
+        ctx.dev = dev;
+        ctx.mode = NOUVEAU_GRCTX_PROG;
+        ctx.data = cp;
+        ctx.ctxprog_max = 256;
+        nv40_grctx_init(&ctx);
+        dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
 
-                cp = kmalloc(sizeof(*cp) * 256, GFP_KERNEL);
-                if (!cp)
-                        return -ENOMEM;
+        nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
+        for (i = 0; i < ctx.ctxprog_len; i++)
+                nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
 
-                ctx.dev = dev;
-                ctx.mode = NOUVEAU_GRCTX_PROG;
-                ctx.data = cp;
-                ctx.ctxprog_max = 256;
-                nv40_grctx_init(&ctx);
-                dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
-
-                nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
-                for (i = 0; i < ctx.ctxprog_len; i++)
-                        nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
-
-                kfree(cp);
-        }
+        kfree(cp);
 
         /* No context present currently */
         nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
@@ -407,7 +392,6 @@ nv40_graph_init(struct drm_device *dev)
 
 void nv40_graph_takedown(struct drm_device *dev)
 {
-        nouveau_grctx_fini(dev);
 }
 
 struct nouveau_pgraph_object_class nv40_graph_grclass[] = {