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authorFrancisco Jerez <currojerez@riseup.net>2009-12-16 06:12:27 -0500
committerDave Airlie <airlied@redhat.com>2010-01-10 23:41:03 -0500
commit0d87c100312ce75d9bb75a456d8a542e84a1722f (patch)
tree8b3820900997e3b50f2e015cdcdd1932c5cab173 /drivers/gpu/drm/nouveau/nv40_graph.c
parent617e234b01757698ed5f8c9a5fbf12717b76e371 (diff)
drm/nouveau: Pre-G80 tiling support.
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv40_graph.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv40_graph.c116
1 files changed, 47 insertions, 69 deletions
diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c
index 2b332bb55acf..53e8afe1dcd1 100644
--- a/drivers/gpu/drm/nouveau/nv40_graph.c
+++ b/drivers/gpu/drm/nouveau/nv40_graph.c
@@ -181,6 +181,48 @@ nv40_graph_unload_context(struct drm_device *dev)
181 return ret; 181 return ret;
182} 182}
183 183
184void
185nv40_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
186 uint32_t size, uint32_t pitch)
187{
188 struct drm_nouveau_private *dev_priv = dev->dev_private;
189 uint32_t limit = max(1u, addr + size) - 1;
190
191 if (pitch)
192 addr |= 1;
193
194 switch (dev_priv->chipset) {
195 case 0x44:
196 case 0x4a:
197 case 0x4e:
198 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
199 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
200 nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
201 break;
202
203 case 0x46:
204 case 0x47:
205 case 0x49:
206 case 0x4b:
207 nv_wr32(dev, NV47_PGRAPH_TSIZE(i), pitch);
208 nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), limit);
209 nv_wr32(dev, NV47_PGRAPH_TILE(i), addr);
210 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch);
211 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit);
212 nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr);
213 break;
214
215 default:
216 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch);
217 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit);
218 nv_wr32(dev, NV20_PGRAPH_TILE(i), addr);
219 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch);
220 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit);
221 nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr);
222 break;
223 }
224}
225
184/* 226/*
185 * G70 0x47 227 * G70 0x47
186 * G71 0x49 228 * G71 0x49
@@ -195,7 +237,8 @@ nv40_graph_init(struct drm_device *dev)
195{ 237{
196 struct drm_nouveau_private *dev_priv = 238 struct drm_nouveau_private *dev_priv =
197 (struct drm_nouveau_private *)dev->dev_private; 239 (struct drm_nouveau_private *)dev->dev_private;
198 uint32_t vramsz, tmp; 240 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
241 uint32_t vramsz;
199 int i, j; 242 int i, j;
200 243
201 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & 244 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
@@ -292,74 +335,9 @@ nv40_graph_init(struct drm_device *dev)
292 nv_wr32(dev, 0x400b38, 0x2ffff800); 335 nv_wr32(dev, 0x400b38, 0x2ffff800);
293 nv_wr32(dev, 0x400b3c, 0x00006000); 336 nv_wr32(dev, 0x400b3c, 0x00006000);
294 337
295 /* copy tile info from PFB */ 338 /* Turn all the tiling regions off. */
296 switch (dev_priv->chipset) { 339 for (i = 0; i < pfb->num_tiles; i++)
297 case 0x40: /* vanilla NV40 */ 340 nv40_graph_set_region_tiling(dev, i, 0, 0, 0);
298 for (i = 0; i < NV10_PFB_TILE__SIZE; i++) {
299 tmp = nv_rd32(dev, NV10_PFB_TILE(i));
300 nv_wr32(dev, NV40_PGRAPH_TILE0(i), tmp);
301 nv_wr32(dev, NV40_PGRAPH_TILE1(i), tmp);
302 tmp = nv_rd32(dev, NV10_PFB_TLIMIT(i));
303 nv_wr32(dev, NV40_PGRAPH_TLIMIT0(i), tmp);
304 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tmp);
305 tmp = nv_rd32(dev, NV10_PFB_TSIZE(i));
306 nv_wr32(dev, NV40_PGRAPH_TSIZE0(i), tmp);
307 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tmp);
308 tmp = nv_rd32(dev, NV10_PFB_TSTATUS(i));
309 nv_wr32(dev, NV40_PGRAPH_TSTATUS0(i), tmp);
310 nv_wr32(dev, NV40_PGRAPH_TSTATUS1(i), tmp);
311 }
312 break;
313 case 0x44:
314 case 0x4a:
315 case 0x4e: /* NV44-based cores don't have 0x406900? */
316 for (i = 0; i < NV40_PFB_TILE__SIZE_0; i++) {
317 tmp = nv_rd32(dev, NV40_PFB_TILE(i));
318 nv_wr32(dev, NV40_PGRAPH_TILE0(i), tmp);
319 tmp = nv_rd32(dev, NV40_PFB_TLIMIT(i));
320 nv_wr32(dev, NV40_PGRAPH_TLIMIT0(i), tmp);
321 tmp = nv_rd32(dev, NV40_PFB_TSIZE(i));
322 nv_wr32(dev, NV40_PGRAPH_TSIZE0(i), tmp);
323 tmp = nv_rd32(dev, NV40_PFB_TSTATUS(i));
324 nv_wr32(dev, NV40_PGRAPH_TSTATUS0(i), tmp);
325 }
326 break;
327 case 0x46:
328 case 0x47:
329 case 0x49:
330 case 0x4b: /* G7X-based cores */
331 for (i = 0; i < NV40_PFB_TILE__SIZE_1; i++) {
332 tmp = nv_rd32(dev, NV40_PFB_TILE(i));
333 nv_wr32(dev, NV47_PGRAPH_TILE0(i), tmp);
334 nv_wr32(dev, NV40_PGRAPH_TILE1(i), tmp);
335 tmp = nv_rd32(dev, NV40_PFB_TLIMIT(i));
336 nv_wr32(dev, NV47_PGRAPH_TLIMIT0(i), tmp);
337 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tmp);
338 tmp = nv_rd32(dev, NV40_PFB_TSIZE(i));
339 nv_wr32(dev, NV47_PGRAPH_TSIZE0(i), tmp);
340 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tmp);
341 tmp = nv_rd32(dev, NV40_PFB_TSTATUS(i));
342 nv_wr32(dev, NV47_PGRAPH_TSTATUS0(i), tmp);
343 nv_wr32(dev, NV40_PGRAPH_TSTATUS1(i), tmp);
344 }
345 break;
346 default: /* everything else */
347 for (i = 0; i < NV40_PFB_TILE__SIZE_0; i++) {
348 tmp = nv_rd32(dev, NV40_PFB_TILE(i));
349 nv_wr32(dev, NV40_PGRAPH_TILE0(i), tmp);
350 nv_wr32(dev, NV40_PGRAPH_TILE1(i), tmp);
351 tmp = nv_rd32(dev, NV40_PFB_TLIMIT(i));
352 nv_wr32(dev, NV40_PGRAPH_TLIMIT0(i), tmp);
353 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tmp);
354 tmp = nv_rd32(dev, NV40_PFB_TSIZE(i));
355 nv_wr32(dev, NV40_PGRAPH_TSIZE0(i), tmp);
356 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tmp);
357 tmp = nv_rd32(dev, NV40_PFB_TSTATUS(i));
358 nv_wr32(dev, NV40_PGRAPH_TSTATUS0(i), tmp);
359 nv_wr32(dev, NV40_PGRAPH_TSTATUS1(i), tmp);
360 }
361 break;
362 }
363 341
364 /* begin RAM config */ 342 /* begin RAM config */
365 vramsz = drm_get_resource_len(dev, 0) - 1; 343 vramsz = drm_get_resource_len(dev, 0) - 1;
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 09:32:11 -0400