diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2012-05-01 06:48:08 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2012-05-24 02:56:11 -0400 |
commit | c420b2dc8dc3cdd507214f4df5c5f96f08812cbe (patch) | |
tree | 6dca9f0aba3de22a2bda5fe647d6945d4f4e986e /drivers/gpu/drm/nouveau/nv04_graph.c | |
parent | a226c32a386bca0426e500954b79e3fd46afc0d9 (diff) |
drm/nouveau/fifo: turn all fifo modules into engine modules
Been tested on each major revision that's relevant here, but I'm sure there
are still bugs waiting to be ironed out.
This is a *very* invasive change.
There's a couple of pieces left that I don't like much (eg. other engines
using fifo_priv for the channel count), but that's an artefact of there
being a master channel list still. This is changing, slowly.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv04_graph.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nv04_graph.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/drivers/gpu/drm/nouveau/nv04_graph.c b/drivers/gpu/drm/nouveau/nv04_graph.c index 5b5f3ba85f5c..72f1a62903b3 100644 --- a/drivers/gpu/drm/nouveau/nv04_graph.c +++ b/drivers/gpu/drm/nouveau/nv04_graph.c | |||
@@ -356,12 +356,12 @@ static struct nouveau_channel * | |||
356 | nv04_graph_channel(struct drm_device *dev) | 356 | nv04_graph_channel(struct drm_device *dev) |
357 | { | 357 | { |
358 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 358 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
359 | int chid = dev_priv->engine.fifo.channels; | 359 | int chid = 15; |
360 | 360 | ||
361 | if (nv_rd32(dev, NV04_PGRAPH_CTX_CONTROL) & 0x00010000) | 361 | if (nv_rd32(dev, NV04_PGRAPH_CTX_CONTROL) & 0x00010000) |
362 | chid = nv_rd32(dev, NV04_PGRAPH_CTX_USER) >> 24; | 362 | chid = nv_rd32(dev, NV04_PGRAPH_CTX_USER) >> 24; |
363 | 363 | ||
364 | if (chid >= dev_priv->engine.fifo.channels) | 364 | if (chid > 15) |
365 | return NULL; | 365 | return NULL; |
366 | 366 | ||
367 | return dev_priv->channels.ptr[chid]; | 367 | return dev_priv->channels.ptr[chid]; |
@@ -404,7 +404,6 @@ nv04_graph_load_context(struct nouveau_channel *chan) | |||
404 | static int | 404 | static int |
405 | nv04_graph_unload_context(struct drm_device *dev) | 405 | nv04_graph_unload_context(struct drm_device *dev) |
406 | { | 406 | { |
407 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
408 | struct nouveau_channel *chan = NULL; | 407 | struct nouveau_channel *chan = NULL; |
409 | struct graph_state *ctx; | 408 | struct graph_state *ctx; |
410 | uint32_t tmp; | 409 | uint32_t tmp; |
@@ -420,7 +419,7 @@ nv04_graph_unload_context(struct drm_device *dev) | |||
420 | 419 | ||
421 | nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL, 0x10000000); | 420 | nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL, 0x10000000); |
422 | tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff; | 421 | tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff; |
423 | tmp |= (dev_priv->engine.fifo.channels - 1) << 24; | 422 | tmp |= 15 << 24; |
424 | nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp); | 423 | nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp); |
425 | return 0; | 424 | return 0; |
426 | } | 425 | } |
@@ -495,7 +494,6 @@ nv04_graph_object_new(struct nouveau_channel *chan, int engine, | |||
495 | static int | 494 | static int |
496 | nv04_graph_init(struct drm_device *dev, int engine) | 495 | nv04_graph_init(struct drm_device *dev, int engine) |
497 | { | 496 | { |
498 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
499 | uint32_t tmp; | 497 | uint32_t tmp; |
500 | 498 | ||
501 | nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & | 499 | nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & |
@@ -527,7 +525,7 @@ nv04_graph_init(struct drm_device *dev, int engine) | |||
527 | nv_wr32(dev, NV04_PGRAPH_STATE , 0xFFFFFFFF); | 525 | nv_wr32(dev, NV04_PGRAPH_STATE , 0xFFFFFFFF); |
528 | nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL , 0x10000100); | 526 | nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL , 0x10000100); |
529 | tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff; | 527 | tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff; |
530 | tmp |= (dev_priv->engine.fifo.channels - 1) << 24; | 528 | tmp |= 15 << 24; |
531 | nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp); | 529 | nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp); |
532 | 530 | ||
533 | /* These don't belong here, they're part of a per-channel context */ | 531 | /* These don't belong here, they're part of a per-channel context */ |