diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2014-08-09 14:10:22 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2014-08-09 15:13:11 -0400 |
commit | db2bec187dd68e79d512112df1f6e7a849e7f0ce (patch) | |
tree | 1a43c57fcea7915c837d5338d2bdf103259bc7be /drivers/gpu/drm/nouveau/dispnv04/overlay.c | |
parent | fa2bade99a6fb24c3847d48ba3cad9a70dbb5364 (diff) |
drm/nouveau: kill nouveau_dev() + wrap register macros
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/dispnv04/overlay.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/dispnv04/overlay.c | 110 |
1 files changed, 55 insertions, 55 deletions
diff --git a/drivers/gpu/drm/nouveau/dispnv04/overlay.c b/drivers/gpu/drm/nouveau/dispnv04/overlay.c index fa69ef011992..bae8068b897f 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/overlay.c +++ b/drivers/gpu/drm/nouveau/dispnv04/overlay.c | |||
@@ -96,7 +96,7 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, | |||
96 | uint32_t src_x, uint32_t src_y, | 96 | uint32_t src_x, uint32_t src_y, |
97 | uint32_t src_w, uint32_t src_h) | 97 | uint32_t src_w, uint32_t src_h) |
98 | { | 98 | { |
99 | struct nouveau_device *dev = nouveau_dev(plane->dev); | 99 | struct nouveau_object *dev = nouveau_drm(plane->dev)->device; |
100 | struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane; | 100 | struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane; |
101 | struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); | 101 | struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); |
102 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | 102 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
@@ -117,7 +117,7 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, | |||
117 | if (format > 0xffff) | 117 | if (format > 0xffff) |
118 | return -ERANGE; | 118 | return -ERANGE; |
119 | 119 | ||
120 | if (dev->chipset >= 0x30) { | 120 | if (nv_device(dev)->chipset >= 0x30) { |
121 | if (crtc_w < (src_w >> 1) || crtc_h < (src_h >> 1)) | 121 | if (crtc_w < (src_w >> 1) || crtc_h < (src_h >> 1)) |
122 | return -ERANGE; | 122 | return -ERANGE; |
123 | } else { | 123 | } else { |
@@ -131,17 +131,17 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, | |||
131 | 131 | ||
132 | nv_plane->cur = nv_fb->nvbo; | 132 | nv_plane->cur = nv_fb->nvbo; |
133 | 133 | ||
134 | nv_mask(dev, NV_PCRTC_ENGINE_CTRL + soff, NV_CRTC_FSEL_OVERLAY, NV_CRTC_FSEL_OVERLAY); | 134 | nvif_mask(dev, NV_PCRTC_ENGINE_CTRL + soff, NV_CRTC_FSEL_OVERLAY, NV_CRTC_FSEL_OVERLAY); |
135 | nv_mask(dev, NV_PCRTC_ENGINE_CTRL + soff2, NV_CRTC_FSEL_OVERLAY, 0); | 135 | nvif_mask(dev, NV_PCRTC_ENGINE_CTRL + soff2, NV_CRTC_FSEL_OVERLAY, 0); |
136 | 136 | ||
137 | nv_wr32(dev, NV_PVIDEO_BASE(flip), 0); | 137 | nvif_wr32(dev, NV_PVIDEO_BASE(flip), 0); |
138 | nv_wr32(dev, NV_PVIDEO_OFFSET_BUFF(flip), nv_fb->nvbo->bo.offset); | 138 | nvif_wr32(dev, NV_PVIDEO_OFFSET_BUFF(flip), nv_fb->nvbo->bo.offset); |
139 | nv_wr32(dev, NV_PVIDEO_SIZE_IN(flip), src_h << 16 | src_w); | 139 | nvif_wr32(dev, NV_PVIDEO_SIZE_IN(flip), src_h << 16 | src_w); |
140 | nv_wr32(dev, NV_PVIDEO_POINT_IN(flip), src_y << 16 | src_x); | 140 | nvif_wr32(dev, NV_PVIDEO_POINT_IN(flip), src_y << 16 | src_x); |
141 | nv_wr32(dev, NV_PVIDEO_DS_DX(flip), (src_w << 20) / crtc_w); | 141 | nvif_wr32(dev, NV_PVIDEO_DS_DX(flip), (src_w << 20) / crtc_w); |
142 | nv_wr32(dev, NV_PVIDEO_DT_DY(flip), (src_h << 20) / crtc_h); | 142 | nvif_wr32(dev, NV_PVIDEO_DT_DY(flip), (src_h << 20) / crtc_h); |
143 | nv_wr32(dev, NV_PVIDEO_POINT_OUT(flip), crtc_y << 16 | crtc_x); | 143 | nvif_wr32(dev, NV_PVIDEO_POINT_OUT(flip), crtc_y << 16 | crtc_x); |
144 | nv_wr32(dev, NV_PVIDEO_SIZE_OUT(flip), crtc_h << 16 | crtc_w); | 144 | nvif_wr32(dev, NV_PVIDEO_SIZE_OUT(flip), crtc_h << 16 | crtc_w); |
145 | 145 | ||
146 | if (fb->pixel_format != DRM_FORMAT_UYVY) | 146 | if (fb->pixel_format != DRM_FORMAT_UYVY) |
147 | format |= NV_PVIDEO_FORMAT_COLOR_LE_CR8YB8CB8YA8; | 147 | format |= NV_PVIDEO_FORMAT_COLOR_LE_CR8YB8CB8YA8; |
@@ -153,14 +153,14 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, | |||
153 | format |= NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY; | 153 | format |= NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY; |
154 | 154 | ||
155 | if (fb->pixel_format == DRM_FORMAT_NV12) { | 155 | if (fb->pixel_format == DRM_FORMAT_NV12) { |
156 | nv_wr32(dev, NV_PVIDEO_UVPLANE_BASE(flip), 0); | 156 | nvif_wr32(dev, NV_PVIDEO_UVPLANE_BASE(flip), 0); |
157 | nv_wr32(dev, NV_PVIDEO_UVPLANE_OFFSET_BUFF(flip), | 157 | nvif_wr32(dev, NV_PVIDEO_UVPLANE_OFFSET_BUFF(flip), |
158 | nv_fb->nvbo->bo.offset + fb->offsets[1]); | 158 | nv_fb->nvbo->bo.offset + fb->offsets[1]); |
159 | } | 159 | } |
160 | nv_wr32(dev, NV_PVIDEO_FORMAT(flip), format); | 160 | nvif_wr32(dev, NV_PVIDEO_FORMAT(flip), format); |
161 | nv_wr32(dev, NV_PVIDEO_STOP, 0); | 161 | nvif_wr32(dev, NV_PVIDEO_STOP, 0); |
162 | /* TODO: wait for vblank? */ | 162 | /* TODO: wait for vblank? */ |
163 | nv_wr32(dev, NV_PVIDEO_BUFFER, flip ? 0x10 : 0x1); | 163 | nvif_wr32(dev, NV_PVIDEO_BUFFER, flip ? 0x10 : 0x1); |
164 | nv_plane->flip = !flip; | 164 | nv_plane->flip = !flip; |
165 | 165 | ||
166 | if (cur) | 166 | if (cur) |
@@ -172,10 +172,10 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, | |||
172 | static int | 172 | static int |
173 | nv10_disable_plane(struct drm_plane *plane) | 173 | nv10_disable_plane(struct drm_plane *plane) |
174 | { | 174 | { |
175 | struct nouveau_device *dev = nouveau_dev(plane->dev); | 175 | struct nouveau_object *dev = nouveau_drm(plane->dev)->device; |
176 | struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane; | 176 | struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane; |
177 | 177 | ||
178 | nv_wr32(dev, NV_PVIDEO_STOP, 1); | 178 | nvif_wr32(dev, NV_PVIDEO_STOP, 1); |
179 | if (nv_plane->cur) { | 179 | if (nv_plane->cur) { |
180 | nouveau_bo_unpin(nv_plane->cur); | 180 | nouveau_bo_unpin(nv_plane->cur); |
181 | nv_plane->cur = NULL; | 181 | nv_plane->cur = NULL; |
@@ -195,24 +195,24 @@ nv_destroy_plane(struct drm_plane *plane) | |||
195 | static void | 195 | static void |
196 | nv10_set_params(struct nouveau_plane *plane) | 196 | nv10_set_params(struct nouveau_plane *plane) |
197 | { | 197 | { |
198 | struct nouveau_device *dev = nouveau_dev(plane->base.dev); | 198 | struct nouveau_object *dev = nouveau_drm(plane->base.dev)->device; |
199 | u32 luma = (plane->brightness - 512) << 16 | plane->contrast; | 199 | u32 luma = (plane->brightness - 512) << 16 | plane->contrast; |
200 | u32 chroma = ((sin_mul(plane->hue, plane->saturation) & 0xffff) << 16) | | 200 | u32 chroma = ((sin_mul(plane->hue, plane->saturation) & 0xffff) << 16) | |
201 | (cos_mul(plane->hue, plane->saturation) & 0xffff); | 201 | (cos_mul(plane->hue, plane->saturation) & 0xffff); |
202 | u32 format = 0; | 202 | u32 format = 0; |
203 | 203 | ||
204 | nv_wr32(dev, NV_PVIDEO_LUMINANCE(0), luma); | 204 | nvif_wr32(dev, NV_PVIDEO_LUMINANCE(0), luma); |
205 | nv_wr32(dev, NV_PVIDEO_LUMINANCE(1), luma); | 205 | nvif_wr32(dev, NV_PVIDEO_LUMINANCE(1), luma); |
206 | nv_wr32(dev, NV_PVIDEO_CHROMINANCE(0), chroma); | 206 | nvif_wr32(dev, NV_PVIDEO_CHROMINANCE(0), chroma); |
207 | nv_wr32(dev, NV_PVIDEO_CHROMINANCE(1), chroma); | 207 | nvif_wr32(dev, NV_PVIDEO_CHROMINANCE(1), chroma); |
208 | nv_wr32(dev, NV_PVIDEO_COLOR_KEY, plane->colorkey & 0xffffff); | 208 | nvif_wr32(dev, NV_PVIDEO_COLOR_KEY, plane->colorkey & 0xffffff); |
209 | 209 | ||
210 | if (plane->cur) { | 210 | if (plane->cur) { |
211 | if (plane->iturbt_709) | 211 | if (plane->iturbt_709) |
212 | format |= NV_PVIDEO_FORMAT_MATRIX_ITURBT709; | 212 | format |= NV_PVIDEO_FORMAT_MATRIX_ITURBT709; |
213 | if (plane->colorkey & (1 << 24)) | 213 | if (plane->colorkey & (1 << 24)) |
214 | format |= NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY; | 214 | format |= NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY; |
215 | nv_mask(dev, NV_PVIDEO_FORMAT(plane->flip), | 215 | nvif_mask(dev, NV_PVIDEO_FORMAT(plane->flip), |
216 | NV_PVIDEO_FORMAT_MATRIX_ITURBT709 | | 216 | NV_PVIDEO_FORMAT_MATRIX_ITURBT709 | |
217 | NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY, | 217 | NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY, |
218 | format); | 218 | format); |
@@ -343,7 +343,7 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, | |||
343 | uint32_t src_x, uint32_t src_y, | 343 | uint32_t src_x, uint32_t src_y, |
344 | uint32_t src_w, uint32_t src_h) | 344 | uint32_t src_w, uint32_t src_h) |
345 | { | 345 | { |
346 | struct nouveau_device *dev = nouveau_dev(plane->dev); | 346 | struct nouveau_object *dev = nouveau_drm(plane->dev)->device; |
347 | struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane; | 347 | struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane; |
348 | struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); | 348 | struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); |
349 | struct nouveau_bo *cur = nv_plane->cur; | 349 | struct nouveau_bo *cur = nv_plane->cur; |
@@ -375,43 +375,43 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, | |||
375 | 375 | ||
376 | nv_plane->cur = nv_fb->nvbo; | 376 | nv_plane->cur = nv_fb->nvbo; |
377 | 377 | ||
378 | nv_wr32(dev, NV_PVIDEO_OE_STATE, 0); | 378 | nvif_wr32(dev, NV_PVIDEO_OE_STATE, 0); |
379 | nv_wr32(dev, NV_PVIDEO_SU_STATE, 0); | 379 | nvif_wr32(dev, NV_PVIDEO_SU_STATE, 0); |
380 | nv_wr32(dev, NV_PVIDEO_RM_STATE, 0); | 380 | nvif_wr32(dev, NV_PVIDEO_RM_STATE, 0); |
381 | 381 | ||
382 | for (i = 0; i < 2; i++) { | 382 | for (i = 0; i < 2; i++) { |
383 | nv_wr32(dev, NV_PVIDEO_BUFF0_START_ADDRESS + 4 * i, | 383 | nvif_wr32(dev, NV_PVIDEO_BUFF0_START_ADDRESS + 4 * i, |
384 | nv_fb->nvbo->bo.offset); | 384 | nv_fb->nvbo->bo.offset); |
385 | nv_wr32(dev, NV_PVIDEO_BUFF0_PITCH_LENGTH + 4 * i, pitch); | 385 | nvif_wr32(dev, NV_PVIDEO_BUFF0_PITCH_LENGTH + 4 * i, pitch); |
386 | nv_wr32(dev, NV_PVIDEO_BUFF0_OFFSET + 4 * i, 0); | 386 | nvif_wr32(dev, NV_PVIDEO_BUFF0_OFFSET + 4 * i, 0); |
387 | } | 387 | } |
388 | nv_wr32(dev, NV_PVIDEO_WINDOW_START, crtc_y << 16 | crtc_x); | 388 | nvif_wr32(dev, NV_PVIDEO_WINDOW_START, crtc_y << 16 | crtc_x); |
389 | nv_wr32(dev, NV_PVIDEO_WINDOW_SIZE, crtc_h << 16 | crtc_w); | 389 | nvif_wr32(dev, NV_PVIDEO_WINDOW_SIZE, crtc_h << 16 | crtc_w); |
390 | nv_wr32(dev, NV_PVIDEO_STEP_SIZE, | 390 | nvif_wr32(dev, NV_PVIDEO_STEP_SIZE, |
391 | (uint32_t)(((src_h - 1) << 11) / (crtc_h - 1)) << 16 | (uint32_t)(((src_w - 1) << 11) / (crtc_w - 1))); | 391 | (uint32_t)(((src_h - 1) << 11) / (crtc_h - 1)) << 16 | (uint32_t)(((src_w - 1) << 11) / (crtc_w - 1))); |
392 | 392 | ||
393 | /* It should be possible to convert hue/contrast to this */ | 393 | /* It should be possible to convert hue/contrast to this */ |
394 | nv_wr32(dev, NV_PVIDEO_RED_CSC_OFFSET, 0x69 - brightness); | 394 | nvif_wr32(dev, NV_PVIDEO_RED_CSC_OFFSET, 0x69 - brightness); |
395 | nv_wr32(dev, NV_PVIDEO_GREEN_CSC_OFFSET, 0x3e + brightness); | 395 | nvif_wr32(dev, NV_PVIDEO_GREEN_CSC_OFFSET, 0x3e + brightness); |
396 | nv_wr32(dev, NV_PVIDEO_BLUE_CSC_OFFSET, 0x89 - brightness); | 396 | nvif_wr32(dev, NV_PVIDEO_BLUE_CSC_OFFSET, 0x89 - brightness); |
397 | nv_wr32(dev, NV_PVIDEO_CSC_ADJUST, 0); | 397 | nvif_wr32(dev, NV_PVIDEO_CSC_ADJUST, 0); |
398 | 398 | ||
399 | nv_wr32(dev, NV_PVIDEO_CONTROL_Y, 0x001); /* (BLUR_ON, LINE_HALF) */ | 399 | nvif_wr32(dev, NV_PVIDEO_CONTROL_Y, 0x001); /* (BLUR_ON, LINE_HALF) */ |
400 | nv_wr32(dev, NV_PVIDEO_CONTROL_X, 0x111); /* (WEIGHT_HEAVY, SHARPENING_ON, SMOOTHING_ON) */ | 400 | nvif_wr32(dev, NV_PVIDEO_CONTROL_X, 0x111); /* (WEIGHT_HEAVY, SHARPENING_ON, SMOOTHING_ON) */ |
401 | 401 | ||
402 | nv_wr32(dev, NV_PVIDEO_FIFO_BURST_LENGTH, 0x03); | 402 | nvif_wr32(dev, NV_PVIDEO_FIFO_BURST_LENGTH, 0x03); |
403 | nv_wr32(dev, NV_PVIDEO_FIFO_THRES_SIZE, 0x38); | 403 | nvif_wr32(dev, NV_PVIDEO_FIFO_THRES_SIZE, 0x38); |
404 | 404 | ||
405 | nv_wr32(dev, NV_PVIDEO_KEY, nv_plane->colorkey); | 405 | nvif_wr32(dev, NV_PVIDEO_KEY, nv_plane->colorkey); |
406 | 406 | ||
407 | if (nv_plane->colorkey & (1 << 24)) | 407 | if (nv_plane->colorkey & (1 << 24)) |
408 | overlay |= 0x10; | 408 | overlay |= 0x10; |
409 | if (fb->pixel_format == DRM_FORMAT_YUYV) | 409 | if (fb->pixel_format == DRM_FORMAT_YUYV) |
410 | overlay |= 0x100; | 410 | overlay |= 0x100; |
411 | 411 | ||
412 | nv_wr32(dev, NV_PVIDEO_OVERLAY, overlay); | 412 | nvif_wr32(dev, NV_PVIDEO_OVERLAY, overlay); |
413 | 413 | ||
414 | nv_wr32(dev, NV_PVIDEO_SU_STATE, nv_rd32(dev, NV_PVIDEO_SU_STATE) ^ (1 << 16)); | 414 | nvif_wr32(dev, NV_PVIDEO_SU_STATE, nvif_rd32(dev, NV_PVIDEO_SU_STATE) ^ (1 << 16)); |
415 | 415 | ||
416 | if (cur) | 416 | if (cur) |
417 | nouveau_bo_unpin(cur); | 417 | nouveau_bo_unpin(cur); |
@@ -422,13 +422,13 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, | |||
422 | static int | 422 | static int |
423 | nv04_disable_plane(struct drm_plane *plane) | 423 | nv04_disable_plane(struct drm_plane *plane) |
424 | { | 424 | { |
425 | struct nouveau_device *dev = nouveau_dev(plane->dev); | 425 | struct nouveau_object *dev = nouveau_drm(plane->dev)->device; |
426 | struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane; | 426 | struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane; |
427 | 427 | ||
428 | nv_mask(dev, NV_PVIDEO_OVERLAY, 1, 0); | 428 | nvif_mask(dev, NV_PVIDEO_OVERLAY, 1, 0); |
429 | nv_wr32(dev, NV_PVIDEO_OE_STATE, 0); | 429 | nvif_wr32(dev, NV_PVIDEO_OE_STATE, 0); |
430 | nv_wr32(dev, NV_PVIDEO_SU_STATE, 0); | 430 | nvif_wr32(dev, NV_PVIDEO_SU_STATE, 0); |
431 | nv_wr32(dev, NV_PVIDEO_RM_STATE, 0); | 431 | nvif_wr32(dev, NV_PVIDEO_RM_STATE, 0); |
432 | if (nv_plane->cur) { | 432 | if (nv_plane->cur) { |
433 | nouveau_bo_unpin(nv_plane->cur); | 433 | nouveau_bo_unpin(nv_plane->cur); |
434 | nv_plane->cur = NULL; | 434 | nv_plane->cur = NULL; |
@@ -489,9 +489,9 @@ err: | |||
489 | void | 489 | void |
490 | nouveau_overlay_init(struct drm_device *device) | 490 | nouveau_overlay_init(struct drm_device *device) |
491 | { | 491 | { |
492 | struct nouveau_device *dev = nouveau_dev(device); | 492 | struct nouveau_object *dev = nouveau_drm(device)->device; |
493 | if (dev->chipset < 0x10) | 493 | if (nv_device(dev)->chipset < 0x10) |
494 | nv04_overlay_init(device); | 494 | nv04_overlay_init(device); |
495 | else if (dev->chipset <= 0x40) | 495 | else if (nv_device(dev)->chipset <= 0x40) |
496 | nv10_overlay_init(device); | 496 | nv10_overlay_init(device); |
497 | } | 497 | } |