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authorBen Skeggs <bskeggs@redhat.com>2014-08-09 14:10:25 -0400
committerBen Skeggs <bskeggs@redhat.com>2014-08-09 15:28:06 -0400
commit2c04ae01df38f95dd3e553c85cdac670a80110f5 (patch)
treefbf20ab8598ea25f2df7190bf7b9fff90fc7baee /drivers/gpu/drm/nouveau/core
parent410f3ec63570bea8efe00826a2b83ceb353553b1 (diff)
drm/nv50-/disp: share channel creation between nv50/gf110 impls
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/core')
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/gm107.c10
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nv50.c153
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nv50.h53
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nv84.c10
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nv94.c10
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nva0.c10
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nva3.c10
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c230
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nve0.c10
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c10
10 files changed, 204 insertions, 302 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c b/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c
index a9681df3273c..f93d76e040fe 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c
@@ -35,11 +35,11 @@
35 35
36static struct nouveau_oclass 36static struct nouveau_oclass
37gm107_disp_sclass[] = { 37gm107_disp_sclass[] = {
38 { GM107_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs }, 38 { GM107_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs.base },
39 { GM107_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs }, 39 { GM107_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs.base },
40 { GM107_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs }, 40 { GM107_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs.base },
41 { GM107_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs }, 41 { GM107_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs.base },
42 { GM107_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs }, 42 { GM107_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs.base },
43 {} 43 {}
44}; 44};
45 45
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
index ca8ce9cace7f..4f1ed8928c82 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
@@ -43,14 +43,16 @@
43 * EVO channel base class 43 * EVO channel base class
44 ******************************************************************************/ 44 ******************************************************************************/
45 45
46int 46static int
47nv50_disp_chan_create_(struct nouveau_object *parent, 47nv50_disp_chan_create_(struct nouveau_object *parent,
48 struct nouveau_object *engine, 48 struct nouveau_object *engine,
49 struct nouveau_oclass *oclass, int chid, 49 struct nouveau_oclass *oclass, int head,
50 int length, void **pobject) 50 int length, void **pobject)
51{ 51{
52 const struct nv50_disp_chan_impl *impl = (void *)oclass->ofuncs;
52 struct nv50_disp_base *base = (void *)parent; 53 struct nv50_disp_base *base = (void *)parent;
53 struct nv50_disp_chan *chan; 54 struct nv50_disp_chan *chan;
55 int chid = impl->chid + head;
54 int ret; 56 int ret;
55 57
56 if (base->chan & (1 << chid)) 58 if (base->chan & (1 << chid))
@@ -63,12 +65,14 @@ nv50_disp_chan_create_(struct nouveau_object *parent,
63 chan = *pobject; 65 chan = *pobject;
64 if (ret) 66 if (ret)
65 return ret; 67 return ret;
66
67 chan->chid = chid; 68 chan->chid = chid;
69
70 nv_parent(chan)->object_attach = impl->attach;
71 nv_parent(chan)->object_detach = impl->detach;
68 return 0; 72 return 0;
69} 73}
70 74
71void 75static void
72nv50_disp_chan_destroy(struct nv50_disp_chan *chan) 76nv50_disp_chan_destroy(struct nv50_disp_chan *chan)
73{ 77{
74 struct nv50_disp_base *base = (void *)nv_object(chan)->parent; 78 struct nv50_disp_base *base = (void *)nv_object(chan)->parent;
@@ -115,16 +119,16 @@ nv50_disp_dmac_object_detach(struct nouveau_object *parent, int cookie)
115 nouveau_ramht_remove(base->ramht, cookie); 119 nouveau_ramht_remove(base->ramht, cookie);
116} 120}
117 121
118int 122static int
119nv50_disp_dmac_create_(struct nouveau_object *parent, 123nv50_disp_dmac_create_(struct nouveau_object *parent,
120 struct nouveau_object *engine, 124 struct nouveau_object *engine,
121 struct nouveau_oclass *oclass, u32 pushbuf, int chid, 125 struct nouveau_oclass *oclass, u32 pushbuf, int head,
122 int length, void **pobject) 126 int length, void **pobject)
123{ 127{
124 struct nv50_disp_dmac *dmac; 128 struct nv50_disp_dmac *dmac;
125 int ret; 129 int ret;
126 130
127 ret = nv50_disp_chan_create_(parent, engine, oclass, chid, 131 ret = nv50_disp_chan_create_(parent, engine, oclass, head,
128 length, pobject); 132 length, pobject);
129 dmac = *pobject; 133 dmac = *pobject;
130 if (ret) 134 if (ret)
@@ -397,7 +401,7 @@ nv50_disp_mast_mthd_chan = {
397 } 401 }
398}; 402};
399 403
400static int 404int
401nv50_disp_mast_ctor(struct nouveau_object *parent, 405nv50_disp_mast_ctor(struct nouveau_object *parent,
402 struct nouveau_object *engine, 406 struct nouveau_object *engine,
403 struct nouveau_oclass *oclass, void *data, u32 size, 407 struct nouveau_oclass *oclass, void *data, u32 size,
@@ -416,8 +420,6 @@ nv50_disp_mast_ctor(struct nouveau_object *parent,
416 if (ret) 420 if (ret)
417 return ret; 421 return ret;
418 422
419 nv_parent(mast)->object_attach = nv50_disp_dmac_object_attach;
420 nv_parent(mast)->object_detach = nv50_disp_dmac_object_detach;
421 return 0; 423 return 0;
422} 424}
423 425
@@ -479,14 +481,17 @@ nv50_disp_mast_fini(struct nouveau_object *object, bool suspend)
479 return nv50_disp_chan_fini(&mast->base, suspend); 481 return nv50_disp_chan_fini(&mast->base, suspend);
480} 482}
481 483
482struct nouveau_ofuncs 484struct nv50_disp_chan_impl
483nv50_disp_mast_ofuncs = { 485nv50_disp_mast_ofuncs = {
484 .ctor = nv50_disp_mast_ctor, 486 .base.ctor = nv50_disp_mast_ctor,
485 .dtor = nv50_disp_dmac_dtor, 487 .base.dtor = nv50_disp_dmac_dtor,
486 .init = nv50_disp_mast_init, 488 .base.init = nv50_disp_mast_init,
487 .fini = nv50_disp_mast_fini, 489 .base.fini = nv50_disp_mast_fini,
488 .rd32 = nv50_disp_chan_rd32, 490 .base.rd32 = nv50_disp_chan_rd32,
489 .wr32 = nv50_disp_chan_wr32, 491 .base.wr32 = nv50_disp_chan_wr32,
492 .chid = 0,
493 .attach = nv50_disp_dmac_object_attach,
494 .detach = nv50_disp_dmac_object_detach,
490}; 495};
491 496
492/******************************************************************************* 497/*******************************************************************************
@@ -543,39 +548,40 @@ nv50_disp_sync_mthd_chan = {
543 } 548 }
544}; 549};
545 550
546static int 551int
547nv50_disp_sync_ctor(struct nouveau_object *parent, 552nv50_disp_sync_ctor(struct nouveau_object *parent,
548 struct nouveau_object *engine, 553 struct nouveau_object *engine,
549 struct nouveau_oclass *oclass, void *data, u32 size, 554 struct nouveau_oclass *oclass, void *data, u32 size,
550 struct nouveau_object **pobject) 555 struct nouveau_object **pobject)
551{ 556{
552 struct nv50_display_sync_class *args = data; 557 struct nv50_display_sync_class *args = data;
558 struct nv50_disp_priv *priv = (void *)engine;
553 struct nv50_disp_dmac *dmac; 559 struct nv50_disp_dmac *dmac;
554 int ret; 560 int ret;
555 561
556 if (size < sizeof(*args) || args->head > 1) 562 if (size < sizeof(*args) || args->head >= priv->head.nr)
557 return -EINVAL; 563 return -EINVAL;
558 564
559 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf, 565 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
560 1 + args->head, sizeof(*dmac), 566 args->head, sizeof(*dmac), (void **)&dmac);
561 (void **)&dmac);
562 *pobject = nv_object(dmac); 567 *pobject = nv_object(dmac);
563 if (ret) 568 if (ret)
564 return ret; 569 return ret;
565 570
566 nv_parent(dmac)->object_attach = nv50_disp_dmac_object_attach;
567 nv_parent(dmac)->object_detach = nv50_disp_dmac_object_detach;
568 return 0; 571 return 0;
569} 572}
570 573
571struct nouveau_ofuncs 574struct nv50_disp_chan_impl
572nv50_disp_sync_ofuncs = { 575nv50_disp_sync_ofuncs = {
573 .ctor = nv50_disp_sync_ctor, 576 .base.ctor = nv50_disp_sync_ctor,
574 .dtor = nv50_disp_dmac_dtor, 577 .base.dtor = nv50_disp_dmac_dtor,
575 .init = nv50_disp_dmac_init, 578 .base.init = nv50_disp_dmac_init,
576 .fini = nv50_disp_dmac_fini, 579 .base.fini = nv50_disp_dmac_fini,
577 .rd32 = nv50_disp_chan_rd32, 580 .base.rd32 = nv50_disp_chan_rd32,
578 .wr32 = nv50_disp_chan_wr32, 581 .base.wr32 = nv50_disp_chan_wr32,
582 .chid = 1,
583 .attach = nv50_disp_dmac_object_attach,
584 .detach = nv50_disp_dmac_object_detach,
579}; 585};
580 586
581/******************************************************************************* 587/*******************************************************************************
@@ -620,39 +626,40 @@ nv50_disp_ovly_mthd_chan = {
620 } 626 }
621}; 627};
622 628
623static int 629int
624nv50_disp_ovly_ctor(struct nouveau_object *parent, 630nv50_disp_ovly_ctor(struct nouveau_object *parent,
625 struct nouveau_object *engine, 631 struct nouveau_object *engine,
626 struct nouveau_oclass *oclass, void *data, u32 size, 632 struct nouveau_oclass *oclass, void *data, u32 size,
627 struct nouveau_object **pobject) 633 struct nouveau_object **pobject)
628{ 634{
629 struct nv50_display_ovly_class *args = data; 635 struct nv50_display_ovly_class *args = data;
636 struct nv50_disp_priv *priv = (void *)engine;
630 struct nv50_disp_dmac *dmac; 637 struct nv50_disp_dmac *dmac;
631 int ret; 638 int ret;
632 639
633 if (size < sizeof(*args) || args->head > 1) 640 if (size < sizeof(*args) || args->head >= priv->head.nr)
634 return -EINVAL; 641 return -EINVAL;
635 642
636 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf, 643 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
637 3 + args->head, sizeof(*dmac), 644 args->head, sizeof(*dmac), (void **)&dmac);
638 (void **)&dmac);
639 *pobject = nv_object(dmac); 645 *pobject = nv_object(dmac);
640 if (ret) 646 if (ret)
641 return ret; 647 return ret;
642 648
643 nv_parent(dmac)->object_attach = nv50_disp_dmac_object_attach;
644 nv_parent(dmac)->object_detach = nv50_disp_dmac_object_detach;
645 return 0; 649 return 0;
646} 650}
647 651
648struct nouveau_ofuncs 652struct nv50_disp_chan_impl
649nv50_disp_ovly_ofuncs = { 653nv50_disp_ovly_ofuncs = {
650 .ctor = nv50_disp_ovly_ctor, 654 .base.ctor = nv50_disp_ovly_ctor,
651 .dtor = nv50_disp_dmac_dtor, 655 .base.dtor = nv50_disp_dmac_dtor,
652 .init = nv50_disp_dmac_init, 656 .base.init = nv50_disp_dmac_init,
653 .fini = nv50_disp_dmac_fini, 657 .base.fini = nv50_disp_dmac_fini,
654 .rd32 = nv50_disp_chan_rd32, 658 .base.rd32 = nv50_disp_chan_rd32,
655 .wr32 = nv50_disp_chan_wr32, 659 .base.wr32 = nv50_disp_chan_wr32,
660 .chid = 3,
661 .attach = nv50_disp_dmac_object_attach,
662 .detach = nv50_disp_dmac_object_detach,
656}; 663};
657 664
658/******************************************************************************* 665/*******************************************************************************
@@ -662,14 +669,14 @@ nv50_disp_ovly_ofuncs = {
662static int 669static int
663nv50_disp_pioc_create_(struct nouveau_object *parent, 670nv50_disp_pioc_create_(struct nouveau_object *parent,
664 struct nouveau_object *engine, 671 struct nouveau_object *engine,
665 struct nouveau_oclass *oclass, int chid, 672 struct nouveau_oclass *oclass, int head,
666 int length, void **pobject) 673 int length, void **pobject)
667{ 674{
668 return nv50_disp_chan_create_(parent, engine, oclass, chid, 675 return nv50_disp_chan_create_(parent, engine, oclass, head,
669 length, pobject); 676 length, pobject);
670} 677}
671 678
672static void 679void
673nv50_disp_pioc_dtor(struct nouveau_object *object) 680nv50_disp_pioc_dtor(struct nouveau_object *object)
674{ 681{
675 struct nv50_disp_pioc *pioc = (void *)object; 682 struct nv50_disp_pioc *pioc = (void *)object;
@@ -727,20 +734,21 @@ nv50_disp_pioc_fini(struct nouveau_object *object, bool suspend)
727 * EVO immediate overlay channel objects 734 * EVO immediate overlay channel objects
728 ******************************************************************************/ 735 ******************************************************************************/
729 736
730static int 737int
731nv50_disp_oimm_ctor(struct nouveau_object *parent, 738nv50_disp_oimm_ctor(struct nouveau_object *parent,
732 struct nouveau_object *engine, 739 struct nouveau_object *engine,
733 struct nouveau_oclass *oclass, void *data, u32 size, 740 struct nouveau_oclass *oclass, void *data, u32 size,
734 struct nouveau_object **pobject) 741 struct nouveau_object **pobject)
735{ 742{
736 struct nv50_display_oimm_class *args = data; 743 struct nv50_display_oimm_class *args = data;
744 struct nv50_disp_priv *priv = (void *)engine;
737 struct nv50_disp_pioc *pioc; 745 struct nv50_disp_pioc *pioc;
738 int ret; 746 int ret;
739 747
740 if (size < sizeof(*args) || args->head > 1) 748 if (size < sizeof(*args) || args->head >= priv->head.nr)
741 return -EINVAL; 749 return -EINVAL;
742 750
743 ret = nv50_disp_pioc_create_(parent, engine, oclass, 5 + args->head, 751 ret = nv50_disp_pioc_create_(parent, engine, oclass, args->head,
744 sizeof(*pioc), (void **)&pioc); 752 sizeof(*pioc), (void **)&pioc);
745 *pobject = nv_object(pioc); 753 *pobject = nv_object(pioc);
746 if (ret) 754 if (ret)
@@ -749,34 +757,36 @@ nv50_disp_oimm_ctor(struct nouveau_object *parent,
749 return 0; 757 return 0;
750} 758}
751 759
752struct nouveau_ofuncs 760struct nv50_disp_chan_impl
753nv50_disp_oimm_ofuncs = { 761nv50_disp_oimm_ofuncs = {
754 .ctor = nv50_disp_oimm_ctor, 762 .base.ctor = nv50_disp_oimm_ctor,
755 .dtor = nv50_disp_pioc_dtor, 763 .base.dtor = nv50_disp_pioc_dtor,
756 .init = nv50_disp_pioc_init, 764 .base.init = nv50_disp_pioc_init,
757 .fini = nv50_disp_pioc_fini, 765 .base.fini = nv50_disp_pioc_fini,
758 .rd32 = nv50_disp_chan_rd32, 766 .base.rd32 = nv50_disp_chan_rd32,
759 .wr32 = nv50_disp_chan_wr32, 767 .base.wr32 = nv50_disp_chan_wr32,
768 .chid = 5,
760}; 769};
761 770
762/******************************************************************************* 771/*******************************************************************************
763 * EVO cursor channel objects 772 * EVO cursor channel objects
764 ******************************************************************************/ 773 ******************************************************************************/
765 774
766static int 775int
767nv50_disp_curs_ctor(struct nouveau_object *parent, 776nv50_disp_curs_ctor(struct nouveau_object *parent,
768 struct nouveau_object *engine, 777 struct nouveau_object *engine,
769 struct nouveau_oclass *oclass, void *data, u32 size, 778 struct nouveau_oclass *oclass, void *data, u32 size,
770 struct nouveau_object **pobject) 779 struct nouveau_object **pobject)
771{ 780{
772 struct nv50_display_curs_class *args = data; 781 struct nv50_display_curs_class *args = data;
782 struct nv50_disp_priv *priv = (void *)engine;
773 struct nv50_disp_pioc *pioc; 783 struct nv50_disp_pioc *pioc;
774 int ret; 784 int ret;
775 785
776 if (size < sizeof(*args) || args->head > 1) 786 if (size < sizeof(*args) || args->head >= priv->head.nr)
777 return -EINVAL; 787 return -EINVAL;
778 788
779 ret = nv50_disp_pioc_create_(parent, engine, oclass, 7 + args->head, 789 ret = nv50_disp_pioc_create_(parent, engine, oclass, args->head,
780 sizeof(*pioc), (void **)&pioc); 790 sizeof(*pioc), (void **)&pioc);
781 *pobject = nv_object(pioc); 791 *pobject = nv_object(pioc);
782 if (ret) 792 if (ret)
@@ -785,14 +795,15 @@ nv50_disp_curs_ctor(struct nouveau_object *parent,
785 return 0; 795 return 0;
786} 796}
787 797
788struct nouveau_ofuncs 798struct nv50_disp_chan_impl
789nv50_disp_curs_ofuncs = { 799nv50_disp_curs_ofuncs = {
790 .ctor = nv50_disp_curs_ctor, 800 .base.ctor = nv50_disp_curs_ctor,
791 .dtor = nv50_disp_pioc_dtor, 801 .base.dtor = nv50_disp_pioc_dtor,
792 .init = nv50_disp_pioc_init, 802 .base.init = nv50_disp_pioc_init,
793 .fini = nv50_disp_pioc_fini, 803 .base.fini = nv50_disp_pioc_fini,
794 .rd32 = nv50_disp_chan_rd32, 804 .base.rd32 = nv50_disp_chan_rd32,
795 .wr32 = nv50_disp_chan_wr32, 805 .base.wr32 = nv50_disp_chan_wr32,
806 .chid = 7,
796}; 807};
797 808
798/******************************************************************************* 809/*******************************************************************************
@@ -966,11 +977,11 @@ nv50_disp_base_oclass[] = {
966 977
967static struct nouveau_oclass 978static struct nouveau_oclass
968nv50_disp_sclass[] = { 979nv50_disp_sclass[] = {
969 { NV50_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs }, 980 { NV50_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs.base },
970 { NV50_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs }, 981 { NV50_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs.base },
971 { NV50_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs }, 982 { NV50_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs.base },
972 { NV50_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs }, 983 { NV50_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs.base },
973 { NV50_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs }, 984 { NV50_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs.base },
974 {} 985 {}
975}; 986};
976 987
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
index c0e8b792433a..a1ec6a556187 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
@@ -104,14 +104,18 @@ struct nv50_disp_base {
104 u32 chan; 104 u32 chan;
105}; 105};
106 106
107struct nv50_disp_chan_impl {
108 struct nouveau_ofuncs base;
109 int chid;
110 int (*attach)(struct nouveau_object *, struct nouveau_object *, u32);
111 void (*detach)(struct nouveau_object *, int);
112};
113
107struct nv50_disp_chan { 114struct nv50_disp_chan {
108 struct nouveau_namedb base; 115 struct nouveau_namedb base;
109 int chid; 116 int chid;
110}; 117};
111 118
112int nv50_disp_chan_create_(struct nouveau_object *, struct nouveau_object *,
113 struct nouveau_oclass *, int, int, void **);
114void nv50_disp_chan_destroy(struct nv50_disp_chan *);
115u32 nv50_disp_chan_rd32(struct nouveau_object *, u64); 119u32 nv50_disp_chan_rd32(struct nouveau_object *, u64);
116void nv50_disp_chan_wr32(struct nouveau_object *, u64, u32); 120void nv50_disp_chan_wr32(struct nouveau_object *, u64, u32);
117 121
@@ -120,20 +124,20 @@ void nv50_disp_chan_wr32(struct nouveau_object *, u64, u32);
120#define nv50_disp_chan_fini(a,b) \ 124#define nv50_disp_chan_fini(a,b) \
121 nouveau_namedb_fini(&(a)->base, (b)) 125 nouveau_namedb_fini(&(a)->base, (b))
122 126
123int nv50_disp_dmac_create_(struct nouveau_object *, struct nouveau_object *,
124 struct nouveau_oclass *, u32, int, int, void **);
125void nv50_disp_dmac_dtor(struct nouveau_object *);
126
127struct nv50_disp_dmac { 127struct nv50_disp_dmac {
128 struct nv50_disp_chan base; 128 struct nv50_disp_chan base;
129 struct nouveau_dmaobj *pushdma; 129 struct nouveau_dmaobj *pushdma;
130 u32 push; 130 u32 push;
131}; 131};
132 132
133void nv50_disp_dmac_dtor(struct nouveau_object *);
134
133struct nv50_disp_pioc { 135struct nv50_disp_pioc {
134 struct nv50_disp_chan base; 136 struct nv50_disp_chan base;
135}; 137};
136 138
139void nv50_disp_pioc_dtor(struct nouveau_object *);
140
137struct nv50_disp_mthd_list { 141struct nv50_disp_mthd_list {
138 u32 mthd; 142 u32 mthd;
139 u32 addr; 143 u32 addr;
@@ -154,16 +158,31 @@ struct nv50_disp_mthd_chan {
154 } data[]; 158 } data[];
155}; 159};
156 160
157extern struct nouveau_ofuncs nv50_disp_mast_ofuncs; 161extern struct nv50_disp_chan_impl nv50_disp_mast_ofuncs;
162int nv50_disp_mast_ctor(struct nouveau_object *, struct nouveau_object *,
163 struct nouveau_oclass *, void *, u32,
164 struct nouveau_object **);
158extern const struct nv50_disp_mthd_list nv50_disp_mast_mthd_base; 165extern const struct nv50_disp_mthd_list nv50_disp_mast_mthd_base;
159extern const struct nv50_disp_mthd_list nv50_disp_mast_mthd_sor; 166extern const struct nv50_disp_mthd_list nv50_disp_mast_mthd_sor;
160extern const struct nv50_disp_mthd_list nv50_disp_mast_mthd_pior; 167extern const struct nv50_disp_mthd_list nv50_disp_mast_mthd_pior;
161extern struct nouveau_ofuncs nv50_disp_sync_ofuncs; 168extern struct nv50_disp_chan_impl nv50_disp_sync_ofuncs;
169int nv50_disp_sync_ctor(struct nouveau_object *, struct nouveau_object *,
170 struct nouveau_oclass *, void *, u32,
171 struct nouveau_object **);
162extern const struct nv50_disp_mthd_list nv50_disp_sync_mthd_image; 172extern const struct nv50_disp_mthd_list nv50_disp_sync_mthd_image;
163extern struct nouveau_ofuncs nv50_disp_ovly_ofuncs; 173extern struct nv50_disp_chan_impl nv50_disp_ovly_ofuncs;
174int nv50_disp_ovly_ctor(struct nouveau_object *, struct nouveau_object *,
175 struct nouveau_oclass *, void *, u32,
176 struct nouveau_object **);
164extern const struct nv50_disp_mthd_list nv50_disp_ovly_mthd_base; 177extern const struct nv50_disp_mthd_list nv50_disp_ovly_mthd_base;
165extern struct nouveau_ofuncs nv50_disp_oimm_ofuncs; 178extern struct nv50_disp_chan_impl nv50_disp_oimm_ofuncs;
166extern struct nouveau_ofuncs nv50_disp_curs_ofuncs; 179int nv50_disp_oimm_ctor(struct nouveau_object *, struct nouveau_object *,
180 struct nouveau_oclass *, void *, u32,
181 struct nouveau_object **);
182extern struct nv50_disp_chan_impl nv50_disp_curs_ofuncs;
183int nv50_disp_curs_ctor(struct nouveau_object *, struct nouveau_object *,
184 struct nouveau_oclass *, void *, u32,
185 struct nouveau_object **);
167extern struct nouveau_ofuncs nv50_disp_base_ofuncs; 186extern struct nouveau_ofuncs nv50_disp_base_ofuncs;
168int nv50_disp_base_ctor(struct nouveau_object *, struct nouveau_object *, 187int nv50_disp_base_ctor(struct nouveau_object *, struct nouveau_object *,
169 struct nouveau_oclass *, void *, u32, 188 struct nouveau_oclass *, void *, u32,
@@ -185,16 +204,16 @@ extern struct nouveau_omthds nv84_disp_base_omthds[];
185 204
186extern const struct nv50_disp_mthd_chan nv94_disp_mast_mthd_chan; 205extern const struct nv50_disp_mthd_chan nv94_disp_mast_mthd_chan;
187 206
188extern struct nouveau_ofuncs nvd0_disp_mast_ofuncs; 207extern struct nv50_disp_chan_impl nvd0_disp_mast_ofuncs;
189extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_base; 208extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_base;
190extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_dac; 209extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_dac;
191extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_sor; 210extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_sor;
192extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_pior; 211extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_pior;
193extern struct nouveau_ofuncs nvd0_disp_sync_ofuncs; 212extern struct nv50_disp_chan_impl nvd0_disp_sync_ofuncs;
194extern struct nouveau_ofuncs nvd0_disp_ovly_ofuncs; 213extern struct nv50_disp_chan_impl nvd0_disp_ovly_ofuncs;
195extern const struct nv50_disp_mthd_chan nvd0_disp_sync_mthd_chan; 214extern const struct nv50_disp_mthd_chan nvd0_disp_sync_mthd_chan;
196extern struct nouveau_ofuncs nvd0_disp_oimm_ofuncs; 215extern struct nv50_disp_chan_impl nvd0_disp_oimm_ofuncs;
197extern struct nouveau_ofuncs nvd0_disp_curs_ofuncs; 216extern struct nv50_disp_chan_impl nvd0_disp_curs_ofuncs;
198extern struct nouveau_omthds nvd0_disp_base_omthds[]; 217extern struct nouveau_omthds nvd0_disp_base_omthds[];
199extern struct nouveau_ofuncs nvd0_disp_base_ofuncs; 218extern struct nouveau_ofuncs nvd0_disp_base_ofuncs;
200extern struct nouveau_oclass nvd0_disp_cclass; 219extern struct nouveau_oclass nvd0_disp_cclass;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
index dd59774ad463..43ef1fab52f1 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
@@ -204,11 +204,11 @@ nv84_disp_ovly_mthd_chan = {
204 204
205static struct nouveau_oclass 205static struct nouveau_oclass
206nv84_disp_sclass[] = { 206nv84_disp_sclass[] = {
207 { NV84_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs }, 207 { NV84_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs.base },
208 { NV84_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs }, 208 { NV84_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs.base },
209 { NV84_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs }, 209 { NV84_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs.base },
210 { NV84_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs }, 210 { NV84_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs.base },
211 { NV84_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs }, 211 { NV84_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs.base },
212 {} 212 {}
213}; 213};
214 214
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
index 03a6b2572fac..2e38a79b19ca 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
@@ -63,11 +63,11 @@ nv94_disp_mast_mthd_chan = {
63 63
64static struct nouveau_oclass 64static struct nouveau_oclass
65nv94_disp_sclass[] = { 65nv94_disp_sclass[] = {
66 { NV94_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs }, 66 { NV94_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs.base },
67 { NV94_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs }, 67 { NV94_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs.base },
68 { NV94_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs }, 68 { NV94_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs.base },
69 { NV94_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs }, 69 { NV94_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs.base },
70 { NV94_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs }, 70 { NV94_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs.base },
71 {} 71 {}
72}; 72};
73 73
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c
index ea1b5a7ad3c8..bfd5cf14b0e4 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c
@@ -80,11 +80,11 @@ nva0_disp_ovly_mthd_chan = {
80 80
81static struct nouveau_oclass 81static struct nouveau_oclass
82nva0_disp_sclass[] = { 82nva0_disp_sclass[] = {
83 { NVA0_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs }, 83 { NVA0_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs.base },
84 { NVA0_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs }, 84 { NVA0_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs.base },
85 { NVA0_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs }, 85 { NVA0_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs.base },
86 { NVA0_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs }, 86 { NVA0_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs.base },
87 { NVA0_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs }, 87 { NVA0_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs.base },
88 {} 88 {}
89}; 89};
90 90
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
index 00f38a39e682..4b601c87c318 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
@@ -35,11 +35,11 @@
35 35
36static struct nouveau_oclass 36static struct nouveau_oclass
37nva3_disp_sclass[] = { 37nva3_disp_sclass[] = {
38 { NVA3_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs }, 38 { NVA3_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs.base },
39 { NVA3_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs }, 39 { NVA3_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs.base },
40 { NVA3_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs }, 40 { NVA3_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs.base },
41 { NVA3_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs }, 41 { NVA3_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs.base },
42 { NVA3_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs }, 42 { NVA3_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs.base },
43 {} 43 {}
44}; 44};
45 45
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
index 1ab21691432d..57d6cb3ed0f7 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
@@ -265,30 +265,6 @@ nvd0_disp_mast_mthd_chan = {
265}; 265};
266 266
267static int 267static int
268nvd0_disp_mast_ctor(struct nouveau_object *parent,
269 struct nouveau_object *engine,
270 struct nouveau_oclass *oclass, void *data, u32 size,
271 struct nouveau_object **pobject)
272{
273 struct nv50_display_mast_class *args = data;
274 struct nv50_disp_dmac *mast;
275 int ret;
276
277 if (size < sizeof(*args))
278 return -EINVAL;
279
280 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
281 0, sizeof(*mast), (void **)&mast);
282 *pobject = nv_object(mast);
283 if (ret)
284 return ret;
285
286 nv_parent(mast)->object_attach = nvd0_disp_dmac_object_attach;
287 nv_parent(mast)->object_detach = nvd0_disp_dmac_object_detach;
288 return 0;
289}
290
291static int
292nvd0_disp_mast_init(struct nouveau_object *object) 268nvd0_disp_mast_init(struct nouveau_object *object)
293{ 269{
294 struct nv50_disp_priv *priv = (void *)object->engine; 270 struct nv50_disp_priv *priv = (void *)object->engine;
@@ -342,14 +318,17 @@ nvd0_disp_mast_fini(struct nouveau_object *object, bool suspend)
342 return nv50_disp_chan_fini(&mast->base, suspend); 318 return nv50_disp_chan_fini(&mast->base, suspend);
343} 319}
344 320
345struct nouveau_ofuncs 321struct nv50_disp_chan_impl
346nvd0_disp_mast_ofuncs = { 322nvd0_disp_mast_ofuncs = {
347 .ctor = nvd0_disp_mast_ctor, 323 .base.ctor = nv50_disp_mast_ctor,
348 .dtor = nv50_disp_dmac_dtor, 324 .base.dtor = nv50_disp_dmac_dtor,
349 .init = nvd0_disp_mast_init, 325 .base.init = nvd0_disp_mast_init,
350 .fini = nvd0_disp_mast_fini, 326 .base.fini = nvd0_disp_mast_fini,
351 .rd32 = nv50_disp_chan_rd32, 327 .base.rd32 = nv50_disp_chan_rd32,
352 .wr32 = nv50_disp_chan_wr32, 328 .base.wr32 = nv50_disp_chan_wr32,
329 .chid = 0,
330 .attach = nvd0_disp_dmac_object_attach,
331 .detach = nvd0_disp_dmac_object_detach,
353}; 332};
354 333
355/******************************************************************************* 334/*******************************************************************************
@@ -431,40 +410,17 @@ nvd0_disp_sync_mthd_chan = {
431 } 410 }
432}; 411};
433 412
434static int 413struct nv50_disp_chan_impl
435nvd0_disp_sync_ctor(struct nouveau_object *parent,
436 struct nouveau_object *engine,
437 struct nouveau_oclass *oclass, void *data, u32 size,
438 struct nouveau_object **pobject)
439{
440 struct nv50_display_sync_class *args = data;
441 struct nv50_disp_priv *priv = (void *)engine;
442 struct nv50_disp_dmac *dmac;
443 int ret;
444
445 if (size < sizeof(*args) || args->head >= priv->head.nr)
446 return -EINVAL;
447
448 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
449 1 + args->head, sizeof(*dmac),
450 (void **)&dmac);
451 *pobject = nv_object(dmac);
452 if (ret)
453 return ret;
454
455 nv_parent(dmac)->object_attach = nvd0_disp_dmac_object_attach;
456 nv_parent(dmac)->object_detach = nvd0_disp_dmac_object_detach;
457 return 0;
458}
459
460struct nouveau_ofuncs
461nvd0_disp_sync_ofuncs = { 414nvd0_disp_sync_ofuncs = {
462 .ctor = nvd0_disp_sync_ctor, 415 .base.ctor = nv50_disp_sync_ctor,
463 .dtor = nv50_disp_dmac_dtor, 416 .base.dtor = nv50_disp_dmac_dtor,
464 .init = nvd0_disp_dmac_init, 417 .base.init = nvd0_disp_dmac_init,
465 .fini = nvd0_disp_dmac_fini, 418 .base.fini = nvd0_disp_dmac_fini,
466 .rd32 = nv50_disp_chan_rd32, 419 .base.rd32 = nv50_disp_chan_rd32,
467 .wr32 = nv50_disp_chan_wr32, 420 .base.wr32 = nv50_disp_chan_wr32,
421 .chid = 1,
422 .attach = nvd0_disp_dmac_object_attach,
423 .detach = nvd0_disp_dmac_object_detach,
468}; 424};
469 425
470/******************************************************************************* 426/*******************************************************************************
@@ -533,40 +489,17 @@ nvd0_disp_ovly_mthd_chan = {
533 } 489 }
534}; 490};
535 491
536static int 492struct nv50_disp_chan_impl
537nvd0_disp_ovly_ctor(struct nouveau_object *parent,
538 struct nouveau_object *engine,
539 struct nouveau_oclass *oclass, void *data, u32 size,
540 struct nouveau_object **pobject)
541{
542 struct nv50_display_ovly_class *args = data;
543 struct nv50_disp_priv *priv = (void *)engine;
544 struct nv50_disp_dmac *dmac;
545 int ret;
546
547 if (size < sizeof(*args) || args->head >= priv->head.nr)
548 return -EINVAL;
549
550 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
551 5 + args->head, sizeof(*dmac),
552 (void **)&dmac);
553 *pobject = nv_object(dmac);
554 if (ret)
555 return ret;
556
557 nv_parent(dmac)->object_attach = nvd0_disp_dmac_object_attach;
558 nv_parent(dmac)->object_detach = nvd0_disp_dmac_object_detach;
559 return 0;
560}
561
562struct nouveau_ofuncs
563nvd0_disp_ovly_ofuncs = { 493nvd0_disp_ovly_ofuncs = {
564 .ctor = nvd0_disp_ovly_ctor, 494 .base.ctor = nv50_disp_ovly_ctor,
565 .dtor = nv50_disp_dmac_dtor, 495 .base.dtor = nv50_disp_dmac_dtor,
566 .init = nvd0_disp_dmac_init, 496 .base.init = nvd0_disp_dmac_init,
567 .fini = nvd0_disp_dmac_fini, 497 .base.fini = nvd0_disp_dmac_fini,
568 .rd32 = nv50_disp_chan_rd32, 498 .base.rd32 = nv50_disp_chan_rd32,
569 .wr32 = nv50_disp_chan_wr32, 499 .base.wr32 = nv50_disp_chan_wr32,
500 .chid = 5,
501 .attach = nvd0_disp_dmac_object_attach,
502 .detach = nvd0_disp_dmac_object_detach,
570}; 503};
571 504
572/******************************************************************************* 505/*******************************************************************************
@@ -574,23 +507,6 @@ nvd0_disp_ovly_ofuncs = {
574 ******************************************************************************/ 507 ******************************************************************************/
575 508
576static int 509static int
577nvd0_disp_pioc_create_(struct nouveau_object *parent,
578 struct nouveau_object *engine,
579 struct nouveau_oclass *oclass, int chid,
580 int length, void **pobject)
581{
582 return nv50_disp_chan_create_(parent, engine, oclass, chid,
583 length, pobject);
584}
585
586static void
587nvd0_disp_pioc_dtor(struct nouveau_object *object)
588{
589 struct nv50_disp_pioc *pioc = (void *)object;
590 nv50_disp_chan_destroy(&pioc->base);
591}
592
593static int
594nvd0_disp_pioc_init(struct nouveau_object *object) 510nvd0_disp_pioc_init(struct nouveau_object *object)
595{ 511{
596 struct nv50_disp_priv *priv = (void *)object->engine; 512 struct nv50_disp_priv *priv = (void *)object->engine;
@@ -643,74 +559,30 @@ nvd0_disp_pioc_fini(struct nouveau_object *object, bool suspend)
643 * EVO immediate overlay channel objects 559 * EVO immediate overlay channel objects
644 ******************************************************************************/ 560 ******************************************************************************/
645 561
646static int 562struct nv50_disp_chan_impl
647nvd0_disp_oimm_ctor(struct nouveau_object *parent,
648 struct nouveau_object *engine,
649 struct nouveau_oclass *oclass, void *data, u32 size,
650 struct nouveau_object **pobject)
651{
652 struct nv50_display_oimm_class *args = data;
653 struct nv50_disp_priv *priv = (void *)engine;
654 struct nv50_disp_pioc *pioc;
655 int ret;
656
657 if (size < sizeof(*args) || args->head >= priv->head.nr)
658 return -EINVAL;
659
660 ret = nvd0_disp_pioc_create_(parent, engine, oclass, 9 + args->head,
661 sizeof(*pioc), (void **)&pioc);
662 *pobject = nv_object(pioc);
663 if (ret)
664 return ret;
665
666 return 0;
667}
668
669struct nouveau_ofuncs
670nvd0_disp_oimm_ofuncs = { 563nvd0_disp_oimm_ofuncs = {
671 .ctor = nvd0_disp_oimm_ctor, 564 .base.ctor = nv50_disp_oimm_ctor,
672 .dtor = nvd0_disp_pioc_dtor, 565 .base.dtor = nv50_disp_pioc_dtor,
673 .init = nvd0_disp_pioc_init, 566 .base.init = nvd0_disp_pioc_init,
674 .fini = nvd0_disp_pioc_fini, 567 .base.fini = nvd0_disp_pioc_fini,
675 .rd32 = nv50_disp_chan_rd32, 568 .base.rd32 = nv50_disp_chan_rd32,
676 .wr32 = nv50_disp_chan_wr32, 569 .base.wr32 = nv50_disp_chan_wr32,
570 .chid = 9,
677}; 571};
678 572
679/******************************************************************************* 573/*******************************************************************************
680 * EVO cursor channel objects 574 * EVO cursor channel objects
681 ******************************************************************************/ 575 ******************************************************************************/
682 576
683static int 577struct nv50_disp_chan_impl
684nvd0_disp_curs_ctor(struct nouveau_object *parent,
685 struct nouveau_object *engine,
686 struct nouveau_oclass *oclass, void *data, u32 size,
687 struct nouveau_object **pobject)
688{
689 struct nv50_display_curs_class *args = data;
690 struct nv50_disp_priv *priv = (void *)engine;
691 struct nv50_disp_pioc *pioc;
692 int ret;
693
694 if (size < sizeof(*args) || args->head >= priv->head.nr)
695 return -EINVAL;
696
697 ret = nvd0_disp_pioc_create_(parent, engine, oclass, 13 + args->head,
698 sizeof(*pioc), (void **)&pioc);
699 *pobject = nv_object(pioc);
700 if (ret)
701 return ret;
702
703 return 0;
704}
705
706struct nouveau_ofuncs
707nvd0_disp_curs_ofuncs = { 578nvd0_disp_curs_ofuncs = {
708 .ctor = nvd0_disp_curs_ctor, 579 .base.ctor = nv50_disp_curs_ctor,
709 .dtor = nvd0_disp_pioc_dtor, 580 .base.dtor = nv50_disp_pioc_dtor,
710 .init = nvd0_disp_pioc_init, 581 .base.init = nvd0_disp_pioc_init,
711 .fini = nvd0_disp_pioc_fini, 582 .base.fini = nvd0_disp_pioc_fini,
712 .rd32 = nv50_disp_chan_rd32, 583 .base.rd32 = nv50_disp_chan_rd32,
713 .wr32 = nv50_disp_chan_wr32, 584 .base.wr32 = nv50_disp_chan_wr32,
585 .chid = 13,
714}; 586};
715 587
716/******************************************************************************* 588/*******************************************************************************
@@ -860,11 +732,11 @@ nvd0_disp_base_oclass[] = {
860 732
861static struct nouveau_oclass 733static struct nouveau_oclass
862nvd0_disp_sclass[] = { 734nvd0_disp_sclass[] = {
863 { NVD0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs }, 735 { NVD0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs.base },
864 { NVD0_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs }, 736 { NVD0_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs.base },
865 { NVD0_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs }, 737 { NVD0_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs.base },
866 { NVD0_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs }, 738 { NVD0_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs.base },
867 { NVD0_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs }, 739 { NVD0_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs.base },
868 {} 740 {}
869}; 741};
870 742
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
index 1e5a79a5cc4f..49ab742faae9 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
@@ -200,11 +200,11 @@ nve0_disp_ovly_mthd_chan = {
200 200
201static struct nouveau_oclass 201static struct nouveau_oclass
202nve0_disp_sclass[] = { 202nve0_disp_sclass[] = {
203 { NVE0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs }, 203 { NVE0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs.base },
204 { NVE0_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs }, 204 { NVE0_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs.base },
205 { NVE0_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs }, 205 { NVE0_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs.base },
206 { NVE0_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs }, 206 { NVE0_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs.base },
207 { NVE0_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs }, 207 { NVE0_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs.base },
208 {} 208 {}
209}; 209};
210 210
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
index 198bc4b0d882..448dc912d0ce 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
@@ -35,11 +35,11 @@
35 35
36static struct nouveau_oclass 36static struct nouveau_oclass
37nvf0_disp_sclass[] = { 37nvf0_disp_sclass[] = {
38 { NVF0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs }, 38 { NVF0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs.base },
39 { NVF0_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs }, 39 { NVF0_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs.base },
40 { NVF0_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs }, 40 { NVF0_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs.base },
41 { NVF0_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs }, 41 { NVF0_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs.base },
42 { NVF0_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs }, 42 { NVF0_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs.base },
43 {} 43 {}
44}; 44};
45 45