diff options
author | Steve Longerbeam <slongerbeam@gmail.com> | 2014-12-18 21:00:25 -0500 |
---|---|---|
committer | Philipp Zabel <p.zabel@pengutronix.de> | 2015-01-07 13:15:03 -0500 |
commit | b6835a719aaa5ee6f493c94cb8b1ff9ad13f5a18 (patch) | |
tree | a97e12f8d51dc4d333524e0f0612b75f99987cf7 /drivers/gpu/drm/imx | |
parent | eb10d6355532def3a74aaabd115e2373cca70b9d (diff) |
gpu: ipu-v3: Use videomode in struct ipu_di_signal_cfg
This patch changes struct ipu_di_signal_cfg to use struct videomode
to define video timings and flags.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Diffstat (limited to 'drivers/gpu/drm/imx')
-rw-r--r-- | drivers/gpu/drm/imx/ipuv3-crtc.c | 26 |
1 files changed, 5 insertions, 21 deletions
diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c b/drivers/gpu/drm/imx/ipuv3-crtc.c index 23d69ecb62dd..c1fc3735913d 100644 --- a/drivers/gpu/drm/imx/ipuv3-crtc.c +++ b/drivers/gpu/drm/imx/ipuv3-crtc.c | |||
@@ -153,35 +153,19 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc, | |||
153 | 153 | ||
154 | out_pixel_fmt = ipu_crtc->interface_pix_fmt; | 154 | out_pixel_fmt = ipu_crtc->interface_pix_fmt; |
155 | 155 | ||
156 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | ||
157 | sig_cfg.interlaced = 1; | ||
158 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) | ||
159 | sig_cfg.Hsync_pol = 1; | ||
160 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) | ||
161 | sig_cfg.Vsync_pol = 1; | ||
162 | |||
163 | sig_cfg.enable_pol = 1; | 156 | sig_cfg.enable_pol = 1; |
164 | sig_cfg.clk_pol = 0; | 157 | sig_cfg.clk_pol = 0; |
165 | sig_cfg.width = mode->hdisplay; | ||
166 | sig_cfg.height = mode->vdisplay; | ||
167 | sig_cfg.pixel_fmt = out_pixel_fmt; | 158 | sig_cfg.pixel_fmt = out_pixel_fmt; |
168 | sig_cfg.h_start_width = mode->htotal - mode->hsync_end; | ||
169 | sig_cfg.h_sync_width = mode->hsync_end - mode->hsync_start; | ||
170 | sig_cfg.h_end_width = mode->hsync_start - mode->hdisplay; | ||
171 | |||
172 | sig_cfg.v_start_width = mode->vtotal - mode->vsync_end; | ||
173 | sig_cfg.v_sync_width = mode->vsync_end - mode->vsync_start; | ||
174 | sig_cfg.v_end_width = mode->vsync_start - mode->vdisplay; | ||
175 | sig_cfg.pixelclock = mode->clock * 1000; | ||
176 | sig_cfg.clkflags = ipu_crtc->di_clkflags; | 159 | sig_cfg.clkflags = ipu_crtc->di_clkflags; |
177 | |||
178 | sig_cfg.v_to_h_sync = 0; | 160 | sig_cfg.v_to_h_sync = 0; |
179 | |||
180 | sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin; | 161 | sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin; |
181 | sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin; | 162 | sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin; |
182 | 163 | ||
183 | ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di, sig_cfg.interlaced, | 164 | drm_display_mode_to_videomode(mode, &sig_cfg.mode); |
184 | out_pixel_fmt, mode->hdisplay); | 165 | |
166 | ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di, | ||
167 | mode->flags & DRM_MODE_FLAG_INTERLACE, | ||
168 | out_pixel_fmt, mode->hdisplay); | ||
185 | if (ret) { | 169 | if (ret) { |
186 | dev_err(ipu_crtc->dev, | 170 | dev_err(ipu_crtc->dev, |
187 | "initializing display controller failed with %d\n", | 171 | "initializing display controller failed with %d\n", |