diff options
author | Andy Yan <andy.yan@rock-chips.com> | 2014-12-05 01:23:52 -0500 |
---|---|---|
committer | Philipp Zabel <p.zabel@pengutronix.de> | 2015-01-06 11:36:15 -0500 |
commit | b587833933de39e21b314e3b392ac0f1ec94a97e (patch) | |
tree | fc246d87022cbcf132b999bd40a279b6d30a2d70 /drivers/gpu/drm/imx | |
parent | f853f3daac748daa339bc8b64ba39db82160524a (diff) |
drm: imx: imx-hdmi: make checkpatch happy
CHECK: Alignment should match open parenthesis
+ if ((hdmi->vic == 10) || (hdmi->vic == 11) ||
+ (hdmi->vic == 12) || (hdmi->vic == 13) ||
CHECK: braces {} should be used on all arms of this statement
+ if (hdmi->hdmi_data.video_mode.mdvi)
[...]
+ else {
[...]
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Diffstat (limited to 'drivers/gpu/drm/imx')
-rw-r--r-- | drivers/gpu/drm/imx/imx-hdmi.c | 109 |
1 files changed, 52 insertions, 57 deletions
diff --git a/drivers/gpu/drm/imx/imx-hdmi.c b/drivers/gpu/drm/imx/imx-hdmi.c index ddc53e039530..3f96a5e6670d 100644 --- a/drivers/gpu/drm/imx/imx-hdmi.c +++ b/drivers/gpu/drm/imx/imx-hdmi.c | |||
@@ -163,7 +163,7 @@ static void hdmi_modb(struct imx_hdmi *hdmi, u8 data, u8 mask, unsigned reg) | |||
163 | } | 163 | } |
164 | 164 | ||
165 | static void hdmi_mask_writeb(struct imx_hdmi *hdmi, u8 data, unsigned int reg, | 165 | static void hdmi_mask_writeb(struct imx_hdmi *hdmi, u8 data, unsigned int reg, |
166 | u8 shift, u8 mask) | 166 | u8 shift, u8 mask) |
167 | { | 167 | { |
168 | hdmi_modb(hdmi, data << shift, mask, reg); | 168 | hdmi_modb(hdmi, data << shift, mask, reg); |
169 | } | 169 | } |
@@ -327,7 +327,7 @@ static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk, | |||
327 | } | 327 | } |
328 | 328 | ||
329 | static void hdmi_set_clk_regenerator(struct imx_hdmi *hdmi, | 329 | static void hdmi_set_clk_regenerator(struct imx_hdmi *hdmi, |
330 | unsigned long pixel_clk) | 330 | unsigned long pixel_clk) |
331 | { | 331 | { |
332 | unsigned int clk_n, clk_cts; | 332 | unsigned int clk_n, clk_cts; |
333 | 333 | ||
@@ -338,7 +338,7 @@ static void hdmi_set_clk_regenerator(struct imx_hdmi *hdmi, | |||
338 | 338 | ||
339 | if (!clk_cts) { | 339 | if (!clk_cts) { |
340 | dev_dbg(hdmi->dev, "%s: pixel clock not supported: %lu\n", | 340 | dev_dbg(hdmi->dev, "%s: pixel clock not supported: %lu\n", |
341 | __func__, pixel_clk); | 341 | __func__, pixel_clk); |
342 | return; | 342 | return; |
343 | } | 343 | } |
344 | 344 | ||
@@ -477,13 +477,11 @@ static void imx_hdmi_update_csc_coeffs(struct imx_hdmi *hdmi) | |||
477 | u16 coeff_b = (*csc_coeff)[1][i]; | 477 | u16 coeff_b = (*csc_coeff)[1][i]; |
478 | u16 coeff_c = (*csc_coeff)[2][i]; | 478 | u16 coeff_c = (*csc_coeff)[2][i]; |
479 | 479 | ||
480 | hdmi_writeb(hdmi, coeff_a & 0xff, | 480 | hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); |
481 | HDMI_CSC_COEF_A1_LSB + i * 2); | ||
482 | hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); | 481 | hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); |
483 | hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); | 482 | hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); |
484 | hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); | 483 | hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); |
485 | hdmi_writeb(hdmi, coeff_c & 0xff, | 484 | hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); |
486 | HDMI_CSC_COEF_C1_LSB + i * 2); | ||
487 | hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); | 485 | hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); |
488 | } | 486 | } |
489 | 487 | ||
@@ -535,21 +533,22 @@ static void hdmi_video_packetize(struct imx_hdmi *hdmi) | |||
535 | struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; | 533 | struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; |
536 | u8 val, vp_conf; | 534 | u8 val, vp_conf; |
537 | 535 | ||
538 | if (hdmi_data->enc_out_format == RGB | 536 | if (hdmi_data->enc_out_format == RGB || |
539 | || hdmi_data->enc_out_format == YCBCR444) { | 537 | hdmi_data->enc_out_format == YCBCR444) { |
540 | if (!hdmi_data->enc_color_depth) | 538 | if (!hdmi_data->enc_color_depth) { |
541 | output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; | 539 | output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; |
542 | else if (hdmi_data->enc_color_depth == 8) { | 540 | } else if (hdmi_data->enc_color_depth == 8) { |
543 | color_depth = 4; | 541 | color_depth = 4; |
544 | output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; | 542 | output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; |
545 | } else if (hdmi_data->enc_color_depth == 10) | 543 | } else if (hdmi_data->enc_color_depth == 10) { |
546 | color_depth = 5; | 544 | color_depth = 5; |
547 | else if (hdmi_data->enc_color_depth == 12) | 545 | } else if (hdmi_data->enc_color_depth == 12) { |
548 | color_depth = 6; | 546 | color_depth = 6; |
549 | else if (hdmi_data->enc_color_depth == 16) | 547 | } else if (hdmi_data->enc_color_depth == 16) { |
550 | color_depth = 7; | 548 | color_depth = 7; |
551 | else | 549 | } else { |
552 | return; | 550 | return; |
551 | } | ||
553 | } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) { | 552 | } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) { |
554 | if (!hdmi_data->enc_color_depth || | 553 | if (!hdmi_data->enc_color_depth || |
555 | hdmi_data->enc_color_depth == 8) | 554 | hdmi_data->enc_color_depth == 8) |
@@ -561,8 +560,9 @@ static void hdmi_video_packetize(struct imx_hdmi *hdmi) | |||
561 | else | 560 | else |
562 | return; | 561 | return; |
563 | output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; | 562 | output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; |
564 | } else | 563 | } else { |
565 | return; | 564 | return; |
565 | } | ||
566 | 566 | ||
567 | /* set the packetizer registers */ | 567 | /* set the packetizer registers */ |
568 | val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & | 568 | val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & |
@@ -623,34 +623,34 @@ static void hdmi_video_packetize(struct imx_hdmi *hdmi) | |||
623 | } | 623 | } |
624 | 624 | ||
625 | static inline void hdmi_phy_test_clear(struct imx_hdmi *hdmi, | 625 | static inline void hdmi_phy_test_clear(struct imx_hdmi *hdmi, |
626 | unsigned char bit) | 626 | unsigned char bit) |
627 | { | 627 | { |
628 | hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, | 628 | hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, |
629 | HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); | 629 | HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); |
630 | } | 630 | } |
631 | 631 | ||
632 | static inline void hdmi_phy_test_enable(struct imx_hdmi *hdmi, | 632 | static inline void hdmi_phy_test_enable(struct imx_hdmi *hdmi, |
633 | unsigned char bit) | 633 | unsigned char bit) |
634 | { | 634 | { |
635 | hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET, | 635 | hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET, |
636 | HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0); | 636 | HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0); |
637 | } | 637 | } |
638 | 638 | ||
639 | static inline void hdmi_phy_test_clock(struct imx_hdmi *hdmi, | 639 | static inline void hdmi_phy_test_clock(struct imx_hdmi *hdmi, |
640 | unsigned char bit) | 640 | unsigned char bit) |
641 | { | 641 | { |
642 | hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET, | 642 | hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET, |
643 | HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0); | 643 | HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0); |
644 | } | 644 | } |
645 | 645 | ||
646 | static inline void hdmi_phy_test_din(struct imx_hdmi *hdmi, | 646 | static inline void hdmi_phy_test_din(struct imx_hdmi *hdmi, |
647 | unsigned char bit) | 647 | unsigned char bit) |
648 | { | 648 | { |
649 | hdmi_writeb(hdmi, bit, HDMI_PHY_TST1); | 649 | hdmi_writeb(hdmi, bit, HDMI_PHY_TST1); |
650 | } | 650 | } |
651 | 651 | ||
652 | static inline void hdmi_phy_test_dout(struct imx_hdmi *hdmi, | 652 | static inline void hdmi_phy_test_dout(struct imx_hdmi *hdmi, |
653 | unsigned char bit) | 653 | unsigned char bit) |
654 | { | 654 | { |
655 | hdmi_writeb(hdmi, bit, HDMI_PHY_TST2); | 655 | hdmi_writeb(hdmi, bit, HDMI_PHY_TST2); |
656 | } | 656 | } |
@@ -666,21 +666,21 @@ static bool hdmi_phy_wait_i2c_done(struct imx_hdmi *hdmi, int msec) | |||
666 | } | 666 | } |
667 | 667 | ||
668 | static void __hdmi_phy_i2c_write(struct imx_hdmi *hdmi, unsigned short data, | 668 | static void __hdmi_phy_i2c_write(struct imx_hdmi *hdmi, unsigned short data, |
669 | unsigned char addr) | 669 | unsigned char addr) |
670 | { | 670 | { |
671 | hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); | 671 | hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); |
672 | hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); | 672 | hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); |
673 | hdmi_writeb(hdmi, (unsigned char)(data >> 8), | 673 | hdmi_writeb(hdmi, (unsigned char)(data >> 8), |
674 | HDMI_PHY_I2CM_DATAO_1_ADDR); | 674 | HDMI_PHY_I2CM_DATAO_1_ADDR); |
675 | hdmi_writeb(hdmi, (unsigned char)(data >> 0), | 675 | hdmi_writeb(hdmi, (unsigned char)(data >> 0), |
676 | HDMI_PHY_I2CM_DATAO_0_ADDR); | 676 | HDMI_PHY_I2CM_DATAO_0_ADDR); |
677 | hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, | 677 | hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, |
678 | HDMI_PHY_I2CM_OPERATION_ADDR); | 678 | HDMI_PHY_I2CM_OPERATION_ADDR); |
679 | hdmi_phy_wait_i2c_done(hdmi, 1000); | 679 | hdmi_phy_wait_i2c_done(hdmi, 1000); |
680 | } | 680 | } |
681 | 681 | ||
682 | static int hdmi_phy_i2c_write(struct imx_hdmi *hdmi, unsigned short data, | 682 | static int hdmi_phy_i2c_write(struct imx_hdmi *hdmi, unsigned short data, |
683 | unsigned char addr) | 683 | unsigned char addr) |
684 | { | 684 | { |
685 | __hdmi_phy_i2c_write(hdmi, data, addr); | 685 | __hdmi_phy_i2c_write(hdmi, data, addr); |
686 | return 0; | 686 | return 0; |
@@ -839,7 +839,7 @@ static int hdmi_phy_configure(struct imx_hdmi *hdmi, unsigned char prep, | |||
839 | 839 | ||
840 | hdmi_phy_test_clear(hdmi, 1); | 840 | hdmi_phy_test_clear(hdmi, 1); |
841 | hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2, | 841 | hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2, |
842 | HDMI_PHY_I2CM_SLAVE_ADDR); | 842 | HDMI_PHY_I2CM_SLAVE_ADDR); |
843 | hdmi_phy_test_clear(hdmi, 0); | 843 | hdmi_phy_test_clear(hdmi, 0); |
844 | 844 | ||
845 | /* PLL/MPLL Cfg - always match on final entry */ | 845 | /* PLL/MPLL Cfg - always match on final entry */ |
@@ -857,9 +857,8 @@ static int hdmi_phy_configure(struct imx_hdmi *hdmi, unsigned char prep, | |||
857 | break; | 857 | break; |
858 | 858 | ||
859 | if (i >= ARRAY_SIZE(curr_ctrl)) { | 859 | if (i >= ARRAY_SIZE(curr_ctrl)) { |
860 | dev_err(hdmi->dev, | 860 | dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n", |
861 | "Pixel clock %d - unsupported by HDMI\n", | 861 | hdmi->hdmi_data.video_mode.mpixelclock); |
862 | hdmi->hdmi_data.video_mode.mpixelclock); | ||
863 | return -EINVAL; | 862 | return -EINVAL; |
864 | } | 863 | } |
865 | 864 | ||
@@ -1223,21 +1222,21 @@ static int imx_hdmi_setup(struct imx_hdmi *hdmi, struct drm_display_mode *mode) | |||
1223 | } | 1222 | } |
1224 | 1223 | ||
1225 | if ((hdmi->vic == 6) || (hdmi->vic == 7) || | 1224 | if ((hdmi->vic == 6) || (hdmi->vic == 7) || |
1226 | (hdmi->vic == 21) || (hdmi->vic == 22) || | 1225 | (hdmi->vic == 21) || (hdmi->vic == 22) || |
1227 | (hdmi->vic == 2) || (hdmi->vic == 3) || | 1226 | (hdmi->vic == 2) || (hdmi->vic == 3) || |
1228 | (hdmi->vic == 17) || (hdmi->vic == 18)) | 1227 | (hdmi->vic == 17) || (hdmi->vic == 18)) |
1229 | hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601; | 1228 | hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601; |
1230 | else | 1229 | else |
1231 | hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709; | 1230 | hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709; |
1232 | 1231 | ||
1233 | if ((hdmi->vic == 10) || (hdmi->vic == 11) || | 1232 | if ((hdmi->vic == 10) || (hdmi->vic == 11) || |
1234 | (hdmi->vic == 12) || (hdmi->vic == 13) || | 1233 | (hdmi->vic == 12) || (hdmi->vic == 13) || |
1235 | (hdmi->vic == 14) || (hdmi->vic == 15) || | 1234 | (hdmi->vic == 14) || (hdmi->vic == 15) || |
1236 | (hdmi->vic == 25) || (hdmi->vic == 26) || | 1235 | (hdmi->vic == 25) || (hdmi->vic == 26) || |
1237 | (hdmi->vic == 27) || (hdmi->vic == 28) || | 1236 | (hdmi->vic == 27) || (hdmi->vic == 28) || |
1238 | (hdmi->vic == 29) || (hdmi->vic == 30) || | 1237 | (hdmi->vic == 29) || (hdmi->vic == 30) || |
1239 | (hdmi->vic == 35) || (hdmi->vic == 36) || | 1238 | (hdmi->vic == 35) || (hdmi->vic == 36) || |
1240 | (hdmi->vic == 37) || (hdmi->vic == 38)) | 1239 | (hdmi->vic == 37) || (hdmi->vic == 38)) |
1241 | hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1; | 1240 | hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1; |
1242 | else | 1241 | else |
1243 | hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; | 1242 | hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; |
@@ -1266,9 +1265,9 @@ static int imx_hdmi_setup(struct imx_hdmi *hdmi, struct drm_display_mode *mode) | |||
1266 | imx_hdmi_enable_video_path(hdmi); | 1265 | imx_hdmi_enable_video_path(hdmi); |
1267 | 1266 | ||
1268 | /* not for DVI mode */ | 1267 | /* not for DVI mode */ |
1269 | if (hdmi->hdmi_data.video_mode.mdvi) | 1268 | if (hdmi->hdmi_data.video_mode.mdvi) { |
1270 | dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); | 1269 | dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); |
1271 | else { | 1270 | } else { |
1272 | dev_dbg(hdmi->dev, "%s CEA mode\n", __func__); | 1271 | dev_dbg(hdmi->dev, "%s CEA mode\n", __func__); |
1273 | 1272 | ||
1274 | /* HDMI Initialization Step E - Configure audio */ | 1273 | /* HDMI Initialization Step E - Configure audio */ |
@@ -1525,7 +1524,7 @@ static irqreturn_t imx_hdmi_irq(int irq, void *dev_id) | |||
1525 | dev_dbg(hdmi->dev, "EVENT=plugout\n"); | 1524 | dev_dbg(hdmi->dev, "EVENT=plugout\n"); |
1526 | 1525 | ||
1527 | hdmi_modb(hdmi, HDMI_PHY_HPD, HDMI_PHY_HPD, | 1526 | hdmi_modb(hdmi, HDMI_PHY_HPD, HDMI_PHY_HPD, |
1528 | HDMI_PHY_POL0); | 1527 | HDMI_PHY_POL0); |
1529 | 1528 | ||
1530 | imx_hdmi_poweroff(hdmi); | 1529 | imx_hdmi_poweroff(hdmi); |
1531 | } | 1530 | } |
@@ -1554,7 +1553,7 @@ static int imx_hdmi_register(struct drm_device *drm, struct imx_hdmi *hdmi) | |||
1554 | DRM_MODE_ENCODER_TMDS); | 1553 | DRM_MODE_ENCODER_TMDS); |
1555 | 1554 | ||
1556 | drm_connector_helper_add(&hdmi->connector, | 1555 | drm_connector_helper_add(&hdmi->connector, |
1557 | &imx_hdmi_connector_helper_funcs); | 1556 | &imx_hdmi_connector_helper_funcs); |
1558 | drm_connector_init(drm, &hdmi->connector, &imx_hdmi_connector_funcs, | 1557 | drm_connector_init(drm, &hdmi->connector, &imx_hdmi_connector_funcs, |
1559 | DRM_MODE_CONNECTOR_HDMIA); | 1558 | DRM_MODE_CONNECTOR_HDMIA); |
1560 | 1559 | ||
@@ -1642,40 +1641,36 @@ static int imx_hdmi_bind(struct device *dev, struct device *master, void *data) | |||
1642 | hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr"); | 1641 | hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr"); |
1643 | if (IS_ERR(hdmi->isfr_clk)) { | 1642 | if (IS_ERR(hdmi->isfr_clk)) { |
1644 | ret = PTR_ERR(hdmi->isfr_clk); | 1643 | ret = PTR_ERR(hdmi->isfr_clk); |
1645 | dev_err(hdmi->dev, | 1644 | dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret); |
1646 | "Unable to get HDMI isfr clk: %d\n", ret); | ||
1647 | return ret; | 1645 | return ret; |
1648 | } | 1646 | } |
1649 | 1647 | ||
1650 | ret = clk_prepare_enable(hdmi->isfr_clk); | 1648 | ret = clk_prepare_enable(hdmi->isfr_clk); |
1651 | if (ret) { | 1649 | if (ret) { |
1652 | dev_err(hdmi->dev, | 1650 | dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret); |
1653 | "Cannot enable HDMI isfr clock: %d\n", ret); | ||
1654 | return ret; | 1651 | return ret; |
1655 | } | 1652 | } |
1656 | 1653 | ||
1657 | hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb"); | 1654 | hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb"); |
1658 | if (IS_ERR(hdmi->iahb_clk)) { | 1655 | if (IS_ERR(hdmi->iahb_clk)) { |
1659 | ret = PTR_ERR(hdmi->iahb_clk); | 1656 | ret = PTR_ERR(hdmi->iahb_clk); |
1660 | dev_err(hdmi->dev, | 1657 | dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret); |
1661 | "Unable to get HDMI iahb clk: %d\n", ret); | ||
1662 | goto err_isfr; | 1658 | goto err_isfr; |
1663 | } | 1659 | } |
1664 | 1660 | ||
1665 | ret = clk_prepare_enable(hdmi->iahb_clk); | 1661 | ret = clk_prepare_enable(hdmi->iahb_clk); |
1666 | if (ret) { | 1662 | if (ret) { |
1667 | dev_err(hdmi->dev, | 1663 | dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret); |
1668 | "Cannot enable HDMI iahb clock: %d\n", ret); | ||
1669 | goto err_isfr; | 1664 | goto err_isfr; |
1670 | } | 1665 | } |
1671 | 1666 | ||
1672 | /* Product and revision IDs */ | 1667 | /* Product and revision IDs */ |
1673 | dev_info(dev, | 1668 | dev_info(dev, |
1674 | "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n", | 1669 | "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n", |
1675 | hdmi_readb(hdmi, HDMI_DESIGN_ID), | 1670 | hdmi_readb(hdmi, HDMI_DESIGN_ID), |
1676 | hdmi_readb(hdmi, HDMI_REVISION_ID), | 1671 | hdmi_readb(hdmi, HDMI_REVISION_ID), |
1677 | hdmi_readb(hdmi, HDMI_PRODUCT_ID0), | 1672 | hdmi_readb(hdmi, HDMI_PRODUCT_ID0), |
1678 | hdmi_readb(hdmi, HDMI_PRODUCT_ID1)); | 1673 | hdmi_readb(hdmi, HDMI_PRODUCT_ID1)); |
1679 | 1674 | ||
1680 | initialize_hdmi_ih_mutes(hdmi); | 1675 | initialize_hdmi_ih_mutes(hdmi); |
1681 | 1676 | ||