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authorPaulo Zanoni <paulo.r.zanoni@intel.com>2013-11-27 14:59:22 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-12-10 16:27:16 -0500
commitd62292c8f778772d1b6ec125d461c8c16fdc0417 (patch)
tree229a9f99b90e0f52d7e71bdb1c54f67f0eeab880 /drivers/gpu/drm/i915
parent7125ecb8297a122d60b2b4be9490f49bfadff8e0 (diff)
drm/i915: get a PC8 reference when enabling the power well
In the current code, at haswell_modeset_global_resources, first we decide if we want to enable/disable the power well, then we decide if we want to enable/disable PC8. On the case where we're enabling PC8 this works fine, but on the case where we disable PC8 due to a non-eDP monitor being enabled, we first enable the power well and then disable PC8. Although wrong, this doesn't seem to be causing any problems now, and we don't even see anything in dmesg. But the patches for runtime D3 turn this problem into a real bug, so we need to fix it. This fixes the "modeset-non-lpsp" subtest from the "pm_pc8" test from intel-gpu-tools. v2: - Rebase (i915_disable_power_well). v3: - More reabase. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c15
1 files changed, 13 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 41b6e080e362..cd3f511847ec 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5688,6 +5688,8 @@ static void hsw_set_power_well(struct drm_device *dev,
5688 unsigned long irqflags; 5688 unsigned long irqflags;
5689 uint32_t tmp; 5689 uint32_t tmp;
5690 5690
5691 WARN_ON(dev_priv->pc8.enabled);
5692
5691 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 5693 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5692 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; 5694 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5693 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; 5695 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
@@ -5747,17 +5749,26 @@ static void hsw_set_power_well(struct drm_device *dev,
5747static void __intel_power_well_get(struct drm_device *dev, 5749static void __intel_power_well_get(struct drm_device *dev,
5748 struct i915_power_well *power_well) 5750 struct i915_power_well *power_well)
5749{ 5751{
5750 if (!power_well->count++ && power_well->set) 5752 struct drm_i915_private *dev_priv = dev->dev_private;
5753
5754 if (!power_well->count++ && power_well->set) {
5755 hsw_disable_package_c8(dev_priv);
5751 power_well->set(dev, power_well, true); 5756 power_well->set(dev, power_well, true);
5757 }
5752} 5758}
5753 5759
5754static void __intel_power_well_put(struct drm_device *dev, 5760static void __intel_power_well_put(struct drm_device *dev,
5755 struct i915_power_well *power_well) 5761 struct i915_power_well *power_well)
5756{ 5762{
5763 struct drm_i915_private *dev_priv = dev->dev_private;
5764
5757 WARN_ON(!power_well->count); 5765 WARN_ON(!power_well->count);
5758 5766
5759 if (!--power_well->count && power_well->set && i915_disable_power_well) 5767 if (!--power_well->count && power_well->set &&
5768 i915_disable_power_well) {
5760 power_well->set(dev, power_well, false); 5769 power_well->set(dev, power_well, false);
5770 hsw_enable_package_c8(dev_priv);
5771 }
5761} 5772}
5762 5773
5763void intel_display_power_get(struct drm_device *dev, 5774void intel_display_power_get(struct drm_device *dev,