drm/i915: Only save/restore FBC on the platform that supports FBC

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>

1 files changed, 22 insertions, 19 deletions

diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index ac0d1a73ac22..60a5800fba6e 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -600,14 +600,16 @@ void i915_save_display(struct drm_device *dev)
         }
         /* FIXME: save TV & SDVO state */
 
-        /* FBC state */
-        if (IS_GM45(dev)) {
-                dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
-        } else {
-                dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
-                dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
-                dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
-                dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
+        /* Only save FBC state on the platform that supports FBC */
+        if (I915_HAS_FBC(dev)) {
+                if (IS_GM45(dev)) {
+                        dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
+                } else {
+                        dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
+                        dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
+                        dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
+                        dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
+                }
         }
 
         /* VGA state */
@@ -702,18 +704,19 @@ void i915_restore_display(struct drm_device *dev)
         }
         /* FIXME: restore TV & SDVO state */
 
-        /* FBC info */
-        if (IS_GM45(dev)) {
-                g4x_disable_fbc(dev);
-                I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
-        } else {
-                i8xx_disable_fbc(dev);
-                I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
-                I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
-                I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
-                I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
+        /* only restore FBC info on the platform that supports FBC*/
+        if (I915_HAS_FBC(dev)) {
+                if (IS_GM45(dev)) {
+                        g4x_disable_fbc(dev);
+                        I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
+                } else {
+                        i8xx_disable_fbc(dev);
+                        I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
+                        I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
+                        I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
+                        I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
+                }
         }
-
         /* VGA state */
         if (IS_IRONLAKE(dev))
                 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL);