drm/i915/skl: Implement WaDisablePartialResolveInVc

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2 files changed, 4 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b00d323095af..b610764768d7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1483,6 +1483,7 @@ enum skl_disp_power_wells {
 #define CACHE_MODE_1            0x7004 /* IVB+ */
 #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE     (1<<6)
 #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE     (1<<6)
+#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE    (1<<1)
 
 #define GEN6_BLITTER_ECOSKPD    0x221d0
 #define   GEN6_BLITTER_LOCK_SHIFT                       16
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ad9d7eb86ef6..29873ff2dd8d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -981,6 +981,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
         /* Wa4x4STCOptimizationDisable:skl */
         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 
+        /* WaDisablePartialResolveInVc:skl */
+        WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
+
         return 0;
 }