drm/i915: Fix SNB GT_MODE register setup

On SNB we set up WaSetupGtModeTdRowDispatch:snb early in
gen6_init_clock_gating(). That sets a bit in the GEN6_GT_MODE register.
However later we go and disable all the bits in the same register. And
then we go on to set some other bit. So apparently we never actually
implemented this workaround since the "disable all bits" part was there
already before the w/a got supposedly implemented.

These are the relevant commits:

 commit 6547fbdbfff62c99e4f7b4f985ff8b3454f33b0f
 Author: Daniel Vetter <daniel.vetter@ffwll.ch>
 Date:   Fri Dec 14 23:38:29 2012 +0100

    drm/i915: Implement WaSetupGtModeTdRowDispatch

 commit f8f2ac9a76b0f80a6763ca316116a7bab8486997
 Author: Ben Widawsky <ben@bwidawsk.net>
 Date:   Wed Oct 3 19:34:24 2012 -0700

    drm/i915: Fix GT_MODE default value

So, let's drop the "disable all bits" part, move both writes to
closer proxomity to each other, and name the WIZ hashing bits
appropriately. BSpec is still a bit confused how the bits should
actually be interpreted, but I took the the description for the
high bit since the low bit part only lists values for a single bit.

Also add a comment about our choice of WIZ hashing mode.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2 files changed, 12 insertions, 6 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2f564ce37d2c..071c17d408c8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -798,7 +798,11 @@
 # define ASYNC_FLIP_PERF_DISABLE                        (1 << 14)
 
 #define GEN6_GT_MODE    0x20d0
-#define   GEN6_GT_MODE_HI                               (1 << 9)
+#define   GEN6_WIZ_HASHING(hi, lo)                      (((hi) << 9) | ((lo) << 7))
+#define   GEN6_WIZ_HASHING_8x8                          GEN6_WIZ_HASHING(0, 0)
+#define   GEN6_WIZ_HASHING_8x4                          GEN6_WIZ_HASHING(0, 1)
+#define   GEN6_WIZ_HASHING_16x4                         GEN6_WIZ_HASHING(1, 0)
+#define   GEN6_WIZ_HASHING_MASK                         (GEN6_WIZ_HASHING(1, 1) << 16)
 #define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE             (1 << 5)
 
 #define GFX_MODE        0x02520
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a6b877a4a916..45dd23f12a6f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4661,6 +4661,13 @@ static void gen6_init_clock_gating(struct drm_device *dev)
                 I915_WRITE(GEN6_GT_MODE,
                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
 
+        /*
+         * BSpec recoomends 8x4 when MSAA is used,
+         * however in practice 16x4 seems fastest.
+         */
+        I915_WRITE(GEN6_GT_MODE,
+                   GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
+
         ilk_init_lp_watermarks(dev);
 
         I915_WRITE(CACHE_MODE_0,
@@ -4724,11 +4731,6 @@ static void gen6_init_clock_gating(struct drm_device *dev)
 
         g4x_disable_trickle_feed(dev);
 
-        /* The default value should be 0x200 according to docs, but the two
-         * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
-        I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
-        I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
-
         cpt_init_clock_gating(dev);
 
         gen6_check_mch_setup(dev);