diff options
author | Rodrigo Vivi <rodrigo.vivi@gmail.com> | 2013-05-06 18:37:36 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-05-10 15:56:49 -0400 |
commit | 891348b2bf08d8946e0621bec49802897b28c1c4 (patch) | |
tree | 67c6f95f96180ab43fc4e9a75b243dc3798205b4 /drivers/gpu/drm/i915 | |
parent | b74ea102b746a1e5157d6b0c83f486ad3c6235d1 (diff) |
drm/i915: Enable FBC at Haswell.
This patch introduce Frame Buffer Compression (FBC) support for HSW.
FBC is tied to primary plane A in HSW.
v2: Ville pointed out docs say FBC must be disabled before disabling
the plane on HSW.
v3: Really enabling it by default at HSW.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915')
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 21 |
3 files changed, 16 insertions, 11 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index cd84f774aace..a1a936fd34e0 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c | |||
@@ -319,6 +319,7 @@ static const struct intel_device_info intel_haswell_m_info = { | |||
319 | .is_mobile = 1, | 319 | .is_mobile = 1, |
320 | .has_ddi = 1, | 320 | .has_ddi = 1, |
321 | .has_fpga_dbg = 1, | 321 | .has_fpga_dbg = 1, |
322 | .has_fbc = 1, | ||
322 | }; | 323 | }; |
323 | 324 | ||
324 | static const struct pci_device_id pciidlist[] = { /* aka */ | 325 | static const struct pci_device_id pciidlist[] = { /* aka */ |
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a14fec3a6740..50814ce84a9f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -3518,11 +3518,12 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) | |||
3518 | drm_vblank_off(dev, pipe); | 3518 | drm_vblank_off(dev, pipe); |
3519 | intel_crtc_update_cursor(crtc, false); | 3519 | intel_crtc_update_cursor(crtc, false); |
3520 | 3520 | ||
3521 | intel_disable_plane(dev_priv, plane, pipe); | 3521 | /* FBC must be disabled before disabling the plane on HSW. */ |
3522 | |||
3523 | if (dev_priv->cfb_plane == plane) | 3522 | if (dev_priv->cfb_plane == plane) |
3524 | intel_disable_fbc(dev); | 3523 | intel_disable_fbc(dev); |
3525 | 3524 | ||
3525 | intel_disable_plane(dev_priv, plane, pipe); | ||
3526 | |||
3526 | if (intel_crtc->config.has_pch_encoder) | 3527 | if (intel_crtc->config.has_pch_encoder) |
3527 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | 3528 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); |
3528 | intel_disable_pipe(dev_priv, pipe); | 3529 | intel_disable_pipe(dev_priv, pipe); |
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index fdc2839448a0..10f788b62fa8 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c | |||
@@ -274,12 +274,14 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | |||
274 | IVB_DPFC_CTL_FENCE_EN | | 274 | IVB_DPFC_CTL_FENCE_EN | |
275 | intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT); | 275 | intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT); |
276 | 276 | ||
277 | /* WaFbcAsynchFlipDisableFbcQueue */ | 277 | if (IS_IVYBRIDGE(dev)) { |
278 | I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS); | 278 | /* WaFbcAsynchFlipDisableFbcQueue */ |
279 | /* WaFbcDisableDpfcClockGating */ | 279 | I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS); |
280 | I915_WRITE(ILK_DSPCLK_GATE_D, | 280 | /* WaFbcDisableDpfcClockGating */ |
281 | I915_READ(ILK_DSPCLK_GATE_D) | | 281 | I915_WRITE(ILK_DSPCLK_GATE_D, |
282 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE); | 282 | I915_READ(ILK_DSPCLK_GATE_D) | |
283 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE); | ||
284 | } | ||
283 | 285 | ||
284 | I915_WRITE(SNB_DPFC_CTL_SA, | 286 | I915_WRITE(SNB_DPFC_CTL_SA, |
285 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | 287 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
@@ -476,7 +478,7 @@ void intel_update_fbc(struct drm_device *dev) | |||
476 | if (enable_fbc < 0) { | 478 | if (enable_fbc < 0) { |
477 | DRM_DEBUG_KMS("fbc set to per-chip default\n"); | 479 | DRM_DEBUG_KMS("fbc set to per-chip default\n"); |
478 | enable_fbc = 1; | 480 | enable_fbc = 1; |
479 | if (INTEL_INFO(dev)->gen <= 7) | 481 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
480 | enable_fbc = 0; | 482 | enable_fbc = 0; |
481 | } | 483 | } |
482 | if (!enable_fbc) { | 484 | if (!enable_fbc) { |
@@ -497,7 +499,8 @@ void intel_update_fbc(struct drm_device *dev) | |||
497 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; | 499 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; |
498 | goto out_disable; | 500 | goto out_disable; |
499 | } | 501 | } |
500 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { | 502 | if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) && |
503 | intel_crtc->plane != 0) { | ||
501 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); | 504 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); |
502 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; | 505 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; |
503 | goto out_disable; | 506 | goto out_disable; |
@@ -4544,7 +4547,7 @@ void intel_init_pm(struct drm_device *dev) | |||
4544 | if (I915_HAS_FBC(dev)) { | 4547 | if (I915_HAS_FBC(dev)) { |
4545 | if (HAS_PCH_SPLIT(dev)) { | 4548 | if (HAS_PCH_SPLIT(dev)) { |
4546 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; | 4549 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
4547 | if (IS_IVYBRIDGE(dev)) | 4550 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
4548 | dev_priv->display.enable_fbc = | 4551 | dev_priv->display.enable_fbc = |
4549 | gen7_enable_fbc; | 4552 | gen7_enable_fbc; |
4550 | else | 4553 | else |