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authorJesse Barnes <jbarnes@virtuousgeek.org>2010-11-01 17:12:01 -0400
committerChris Wilson <chris@chris-wilson.co.uk>2010-11-02 05:34:52 -0400
commit80dbf4b72b0bcac71fc683914293555edb7bc7ee (patch)
tree0d18207f1db8ad651eee96680cc470c52464dba3 /drivers/gpu/drm/i915
parent0aa992777270f0ea7097170fa50a1d98615eb0d4 (diff)
drm/i915: Fix the graphics frequency clamping at init and when IPS is active.
Part of the issue here was that Eric slipped in a debug hack for testing the i915 IPS code before the intel_ips.c driver had landed. This caused the driver to always use the full range of frequencies, which is only legal when IPS tells us we have the headroom. Once that hack was removed, there was confusion about the driver's frequency clamping variables: max_delay is the driver's current limit on the highest frequency the IPS driver wants us to use, while dev_priv->fmax is the hardware-reported limit that the IPS driver can increase up to. Tested with IPS driver loaded or not. Note that on Ironlake systems without the IPS driver loaded this will result in a performance reduction, and the inital warmup of frequency limits can impact benchmarking on systems with IPS loaded. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net> [ickle: demoted a debugging printk] Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c9
1 files changed, 4 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 990f065374b2..528aa06d430d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5581,20 +5581,19 @@ void ironlake_enable_drps(struct drm_device *dev)
5581 fmin = (rgvmodectl & MEMMODE_FMIN_MASK); 5581 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5582 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> 5582 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5583 MEMMODE_FSTART_SHIFT; 5583 MEMMODE_FSTART_SHIFT;
5584 fstart = fmax;
5585 5584
5586 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> 5585 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5587 PXVFREQ_PX_SHIFT; 5586 PXVFREQ_PX_SHIFT;
5588 5587
5589 dev_priv->fmax = fstart; /* IPS callback will increase this */ 5588 dev_priv->fmax = fmax; /* IPS callback will increase this */
5590 dev_priv->fstart = fstart; 5589 dev_priv->fstart = fstart;
5591 5590
5592 dev_priv->max_delay = fmax; 5591 dev_priv->max_delay = fstart;
5593 dev_priv->min_delay = fmin; 5592 dev_priv->min_delay = fmin;
5594 dev_priv->cur_delay = fstart; 5593 dev_priv->cur_delay = fstart;
5595 5594
5596 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin, 5595 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
5597 fstart); 5596 fmax, fmin, fstart);
5598 5597
5599 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); 5598 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5600 5599