diff options
author | Ben Widawsky <benjamin.widawsky@intel.com> | 2013-11-03 00:07:47 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-11-08 12:09:59 -0500 |
commit | 2a114cc1b964ba0208aa6858d01cee82ac026ec6 (patch) | |
tree | 36a8d874e57fd4d864d3956735c872b3de3b1b86 /drivers/gpu/drm/i915 | |
parent | 416f4727abf9e5ecc88fea4b55ea294d310534ac (diff) |
drm/i915/bdw: Use The GT mailbox for IPS enable/disable
v2: Squash in fixup from Ben to synchronize the GT mailbox commands.
CC: Art Runyan <arthur.j.runyan@intel.com>
Reviewed-by: Art Runyan <arthur.j.runyan@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915')
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 36 |
3 files changed, 28 insertions, 11 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d9d6db263ab2..5deeb19551a4 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h | |||
@@ -1805,7 +1805,7 @@ struct drm_i915_file_private { | |||
1805 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | 1805 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
1806 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | 1806 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
1807 | 1807 | ||
1808 | #define HAS_IPS(dev) (IS_ULT(dev)) | 1808 | #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev)) |
1809 | 1809 | ||
1810 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) | 1810 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
1811 | #define HAS_POWER_WELL(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) | 1811 | #define HAS_POWER_WELL(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b2abdd78fdef..f99c8c5b7bd0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -4953,6 +4953,7 @@ | |||
4953 | #define GEN6_PCODE_WRITE_D_COMP 0x11 | 4953 | #define GEN6_PCODE_WRITE_D_COMP 0x11 |
4954 | #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) | 4954 | #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) |
4955 | #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) | 4955 | #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) |
4956 | #define DISPLAY_IPS_CONTROL 0x19 | ||
4956 | #define GEN6_PCODE_DATA 0x138128 | 4957 | #define GEN6_PCODE_DATA 0x138128 |
4957 | #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 | 4958 | #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 |
4958 | #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 | 4959 | #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 |
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 1b1e75ed0504..e690cfedd6d5 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -3393,15 +3393,26 @@ void hsw_enable_ips(struct intel_crtc *crtc) | |||
3393 | * only after intel_enable_plane. And intel_enable_plane already waits | 3393 | * only after intel_enable_plane. And intel_enable_plane already waits |
3394 | * for a vblank, so all we need to do here is to enable the IPS bit. */ | 3394 | * for a vblank, so all we need to do here is to enable the IPS bit. */ |
3395 | assert_plane_enabled(dev_priv, crtc->plane); | 3395 | assert_plane_enabled(dev_priv, crtc->plane); |
3396 | I915_WRITE(IPS_CTL, IPS_ENABLE); | 3396 | if (IS_BROADWELL(crtc->base.dev)) { |
3397 | 3397 | mutex_lock(&dev_priv->rps.hw_lock); | |
3398 | /* The bit only becomes 1 in the next vblank, so this wait here is | 3398 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); |
3399 | * essentially intel_wait_for_vblank. If we don't have this and don't | 3399 | mutex_unlock(&dev_priv->rps.hw_lock); |
3400 | * wait for vblanks until the end of crtc_enable, then the HW state | 3400 | /* Quoting Art Runyan: "its not safe to expect any particular |
3401 | * readout code will complain that the expected IPS_CTL value is not the | 3401 | * value in IPS_CTL bit 31 after enabling IPS through the |
3402 | * one we read. */ | 3402 | * mailbox." Therefore we need to defer waiting on the state |
3403 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | 3403 | * change. |
3404 | DRM_ERROR("Timed out waiting for IPS enable\n"); | 3404 | * TODO: need to fix this for state checker |
3405 | */ | ||
3406 | } else { | ||
3407 | I915_WRITE(IPS_CTL, IPS_ENABLE); | ||
3408 | /* The bit only becomes 1 in the next vblank, so this wait here | ||
3409 | * is essentially intel_wait_for_vblank. If we don't have this | ||
3410 | * and don't wait for vblanks until the end of crtc_enable, then | ||
3411 | * the HW state readout code will complain that the expected | ||
3412 | * IPS_CTL value is not the one we read. */ | ||
3413 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | ||
3414 | DRM_ERROR("Timed out waiting for IPS enable\n"); | ||
3415 | } | ||
3405 | } | 3416 | } |
3406 | 3417 | ||
3407 | void hsw_disable_ips(struct intel_crtc *crtc) | 3418 | void hsw_disable_ips(struct intel_crtc *crtc) |
@@ -3413,7 +3424,12 @@ void hsw_disable_ips(struct intel_crtc *crtc) | |||
3413 | return; | 3424 | return; |
3414 | 3425 | ||
3415 | assert_plane_enabled(dev_priv, crtc->plane); | 3426 | assert_plane_enabled(dev_priv, crtc->plane); |
3416 | I915_WRITE(IPS_CTL, 0); | 3427 | if (IS_BROADWELL(crtc->base.dev)) { |
3428 | mutex_lock(&dev_priv->rps.hw_lock); | ||
3429 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | ||
3430 | mutex_unlock(&dev_priv->rps.hw_lock); | ||
3431 | } else | ||
3432 | I915_WRITE(IPS_CTL, 0); | ||
3417 | POSTING_READ(IPS_CTL); | 3433 | POSTING_READ(IPS_CTL); |
3418 | 3434 | ||
3419 | /* We need to wait for a vblank before we can disable the plane. */ | 3435 | /* We need to wait for a vblank before we can disable the plane. */ |