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authorZhenyu Wang <zhenyuw@linux.intel.com>2009-06-05 03:38:37 -0400
committerEric Anholt <eric@anholt.net>2009-06-05 07:34:00 -0400
commit280da227c870a50f669de0c8d46bfb2c62da9995 (patch)
tree5fd455c04c9bc2fa4ae00acab8db382746f54d7a /drivers/gpu/drm/i915
parent32cb055b57eab803ea82b76dc913b0378e5af145 (diff)
drm/i915: Add chipset/feature defines for for new chipsets
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> [anholt: dropped drm_pciids.h hunk to avoid loading an incomplete driver] Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h18
1 files changed, 13 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e0fac5f62c69..ded9e786883e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -796,7 +796,9 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
796 (dev)->pci_device == 0x2E02 || \ 796 (dev)->pci_device == 0x2E02 || \
797 (dev)->pci_device == 0x2E12 || \ 797 (dev)->pci_device == 0x2E12 || \
798 (dev)->pci_device == 0x2E22 || \ 798 (dev)->pci_device == 0x2E22 || \
799 (dev)->pci_device == 0x2E32) 799 (dev)->pci_device == 0x2E32 || \
800 (dev)->pci_device == 0x0042 || \
801 (dev)->pci_device == 0x0046)
800 802
801#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \ 803#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
802 (dev)->pci_device == 0x2A12) 804 (dev)->pci_device == 0x2A12)
@@ -818,20 +820,26 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
818 (dev)->pci_device == 0x29D2 || \ 820 (dev)->pci_device == 0x29D2 || \
819 (IS_IGD(dev))) 821 (IS_IGD(dev)))
820 822
823#define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042)
824#define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046)
825#define IS_IGDNG(dev) (IS_IGDNG_D(dev) || IS_IGDNG_M(dev))
826
821#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 827#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
822 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) 828 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
829 IS_IGDNG(dev))
823 830
824#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ 831#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
825 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \ 832 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
826 IS_IGD(dev)) 833 IS_IGD(dev) || IS_IGDNG_M(dev))
827 834
828#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev)) 835#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
836 IS_IGDNG(dev))
829/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 837/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
830 * rows, which changed the alignment requirements and fence programming. 838 * rows, which changed the alignment requirements and fence programming.
831 */ 839 */
832#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \ 840#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
833 IS_I915GM(dev))) 841 IS_I915GM(dev)))
834#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev)) 842#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev))
835#define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_I965G(dev)) 843#define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_I965G(dev))
836 844
837#define PRIMARY_RINGBUFFER_SIZE (128*1024) 845#define PRIMARY_RINGBUFFER_SIZE (128*1024)