diff options
| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-07-26 02:35:42 -0400 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-07-26 13:54:46 -0400 |
| commit | 257a7ffcfaf68718c963db6e9978d1f4f647986b (patch) | |
| tree | 6be9d1fea506a58abd06bea212531148cfb5488d /drivers/gpu/drm/i915 | |
| parent | de51f04f06d5e4a37f8e5a2b1019eb34140480f0 (diff) | |
drm/i915: fix pnv display core clock readout out
We need the correct clock to accurately assess whether we need to
enable the double wide pipe mode or not.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Stéphane Marchesin <marcheu@chromium.org>
Cc: Stuart Abercrombie <sabercrombie@google.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 29 |
2 files changed, 34 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6caa748fa00f..3aebe5dee4df 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
| @@ -61,6 +61,12 @@ | |||
| 61 | #define GC_LOW_FREQUENCY_ENABLE (1 << 7) | 61 | #define GC_LOW_FREQUENCY_ENABLE (1 << 7) |
| 62 | #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) | 62 | #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) |
| 63 | #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) | 63 | #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) |
| 64 | #define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) | ||
| 65 | #define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) | ||
| 66 | #define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) | ||
| 67 | #define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) | ||
| 68 | #define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) | ||
| 69 | #define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) | ||
| 64 | #define GC_DISPLAY_CLOCK_MASK (7 << 4) | 70 | #define GC_DISPLAY_CLOCK_MASK (7 << 4) |
| 65 | #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) | 71 | #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) |
| 66 | #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) | 72 | #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) |
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b3389d74d695..3e66f05ea342 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
| @@ -4163,6 +4163,30 @@ static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) | |||
| 4163 | return 200000; | 4163 | return 200000; |
| 4164 | } | 4164 | } |
| 4165 | 4165 | ||
| 4166 | static int pnv_get_display_clock_speed(struct drm_device *dev) | ||
| 4167 | { | ||
| 4168 | u16 gcfgc = 0; | ||
| 4169 | |||
| 4170 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | ||
| 4171 | |||
| 4172 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | ||
| 4173 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | ||
| 4174 | return 267000; | ||
| 4175 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | ||
| 4176 | return 333000; | ||
| 4177 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | ||
| 4178 | return 444000; | ||
| 4179 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | ||
| 4180 | return 200000; | ||
| 4181 | default: | ||
| 4182 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | ||
| 4183 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | ||
| 4184 | return 133000; | ||
| 4185 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | ||
| 4186 | return 167000; | ||
| 4187 | } | ||
| 4188 | } | ||
| 4189 | |||
| 4166 | static int i915gm_get_display_clock_speed(struct drm_device *dev) | 4190 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
| 4167 | { | 4191 | { |
| 4168 | u16 gcfgc = 0; | 4192 | u16 gcfgc = 0; |
| @@ -9605,9 +9629,12 @@ static void intel_init_display(struct drm_device *dev) | |||
| 9605 | else if (IS_I915G(dev)) | 9629 | else if (IS_I915G(dev)) |
| 9606 | dev_priv->display.get_display_clock_speed = | 9630 | dev_priv->display.get_display_clock_speed = |
| 9607 | i915_get_display_clock_speed; | 9631 | i915_get_display_clock_speed; |
| 9608 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) | 9632 | else if (IS_I945GM(dev) || IS_845G(dev)) |
| 9609 | dev_priv->display.get_display_clock_speed = | 9633 | dev_priv->display.get_display_clock_speed = |
| 9610 | i9xx_misc_get_display_clock_speed; | 9634 | i9xx_misc_get_display_clock_speed; |
| 9635 | else if (IS_PINEVIEW(dev)) | ||
| 9636 | dev_priv->display.get_display_clock_speed = | ||
| 9637 | pnv_get_display_clock_speed; | ||
| 9611 | else if (IS_I915GM(dev)) | 9638 | else if (IS_I915GM(dev)) |
| 9612 | dev_priv->display.get_display_clock_speed = | 9639 | dev_priv->display.get_display_clock_speed = |
| 9613 | i915gm_get_display_clock_speed; | 9640 | i915gm_get_display_clock_speed; |