diff options
author | Chris Wilson <chris@chris-wilson.co.uk> | 2010-12-14 15:04:54 -0500 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-12-14 15:09:04 -0500 |
commit | 1b894b59247728b02d6363d458088cf438f5ec92 (patch) | |
tree | 5f54aa1e0b12f5f876f0e875e51887e58b68226f /drivers/gpu/drm/i915 | |
parent | b5ba177d8d71f011c23b1cabec99fdaddae65c4d (diff) |
drm/i915: Pass clock limits down to PLL matcher
As we already know the limits for the hardware clock, pass it down
rather than recomputing them for each match.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 34 |
1 files changed, 16 insertions, 18 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 17c213fef0ec..f2d50141e0c2 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -642,26 +642,23 @@ static const intel_limit_t intel_limits_ironlake_display_port = { | |||
642 | .find_pll = intel_find_pll_ironlake_dp, | 642 | .find_pll = intel_find_pll_ironlake_dp, |
643 | }; | 643 | }; |
644 | 644 | ||
645 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc) | 645 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
646 | int refclk) | ||
646 | { | 647 | { |
647 | struct drm_device *dev = crtc->dev; | 648 | struct drm_device *dev = crtc->dev; |
648 | struct drm_i915_private *dev_priv = dev->dev_private; | 649 | struct drm_i915_private *dev_priv = dev->dev_private; |
649 | const intel_limit_t *limit; | 650 | const intel_limit_t *limit; |
650 | int refclk = 120; | ||
651 | 651 | ||
652 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | 652 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
653 | if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100) | ||
654 | refclk = 100; | ||
655 | |||
656 | if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == | 653 | if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == |
657 | LVDS_CLKB_POWER_UP) { | 654 | LVDS_CLKB_POWER_UP) { |
658 | /* LVDS dual channel */ | 655 | /* LVDS dual channel */ |
659 | if (refclk == 100) | 656 | if (refclk == 100000) |
660 | limit = &intel_limits_ironlake_dual_lvds_100m; | 657 | limit = &intel_limits_ironlake_dual_lvds_100m; |
661 | else | 658 | else |
662 | limit = &intel_limits_ironlake_dual_lvds; | 659 | limit = &intel_limits_ironlake_dual_lvds; |
663 | } else { | 660 | } else { |
664 | if (refclk == 100) | 661 | if (refclk == 100000) |
665 | limit = &intel_limits_ironlake_single_lvds_100m; | 662 | limit = &intel_limits_ironlake_single_lvds_100m; |
666 | else | 663 | else |
667 | limit = &intel_limits_ironlake_single_lvds; | 664 | limit = &intel_limits_ironlake_single_lvds; |
@@ -702,13 +699,13 @@ static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) | |||
702 | return limit; | 699 | return limit; |
703 | } | 700 | } |
704 | 701 | ||
705 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc) | 702 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
706 | { | 703 | { |
707 | struct drm_device *dev = crtc->dev; | 704 | struct drm_device *dev = crtc->dev; |
708 | const intel_limit_t *limit; | 705 | const intel_limit_t *limit; |
709 | 706 | ||
710 | if (HAS_PCH_SPLIT(dev)) | 707 | if (HAS_PCH_SPLIT(dev)) |
711 | limit = intel_ironlake_limit(crtc); | 708 | limit = intel_ironlake_limit(crtc, refclk); |
712 | else if (IS_G4X(dev)) { | 709 | else if (IS_G4X(dev)) { |
713 | limit = intel_g4x_limit(crtc); | 710 | limit = intel_g4x_limit(crtc); |
714 | } else if (IS_PINEVIEW(dev)) { | 711 | } else if (IS_PINEVIEW(dev)) { |
@@ -773,11 +770,10 @@ bool intel_pipe_has_type(struct drm_crtc *crtc, int type) | |||
773 | * the given connectors. | 770 | * the given connectors. |
774 | */ | 771 | */ |
775 | 772 | ||
776 | static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock) | 773 | static bool intel_PLL_is_valid(struct drm_device *dev, |
774 | const intel_limit_t *limit, | ||
775 | const intel_clock_t *clock) | ||
777 | { | 776 | { |
778 | const intel_limit_t *limit = intel_limit (crtc); | ||
779 | struct drm_device *dev = crtc->dev; | ||
780 | |||
781 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) | 777 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
782 | INTELPllInvalid ("p1 out of range\n"); | 778 | INTELPllInvalid ("p1 out of range\n"); |
783 | if (clock->p < limit->p.min || limit->p.max < clock->p) | 779 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
@@ -849,8 +845,8 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |||
849 | int this_err; | 845 | int this_err; |
850 | 846 | ||
851 | intel_clock(dev, refclk, &clock); | 847 | intel_clock(dev, refclk, &clock); |
852 | 848 | if (!intel_PLL_is_valid(dev, limit, | |
853 | if (!intel_PLL_is_valid(crtc, &clock)) | 849 | &clock)) |
854 | continue; | 850 | continue; |
855 | 851 | ||
856 | this_err = abs(clock.dot - target); | 852 | this_err = abs(clock.dot - target); |
@@ -912,9 +908,11 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |||
912 | int this_err; | 908 | int this_err; |
913 | 909 | ||
914 | intel_clock(dev, refclk, &clock); | 910 | intel_clock(dev, refclk, &clock); |
915 | if (!intel_PLL_is_valid(crtc, &clock)) | 911 | if (!intel_PLL_is_valid(dev, limit, |
912 | &clock)) | ||
916 | continue; | 913 | continue; |
917 | this_err = abs(clock.dot - target) ; | 914 | |
915 | this_err = abs(clock.dot - target); | ||
918 | if (this_err < err_most) { | 916 | if (this_err < err_most) { |
919 | *best_clock = clock; | 917 | *best_clock = clock; |
920 | err_most = this_err; | 918 | err_most = this_err; |
@@ -3655,7 +3653,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, | |||
3655 | * refclk, or FALSE. The returned values represent the clock equation: | 3653 | * refclk, or FALSE. The returned values represent the clock equation: |
3656 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | 3654 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
3657 | */ | 3655 | */ |
3658 | limit = intel_limit(crtc); | 3656 | limit = intel_limit(crtc, refclk); |
3659 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock); | 3657 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock); |
3660 | if (!ok) { | 3658 | if (!ok) { |
3661 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | 3659 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |