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authorVille Syrjälä <ville.syrjala@linux.intel.com>2014-04-28 08:53:25 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-05-06 04:18:04 -0400
commit10efa9321efe5f62637b189587539e4086726a2b (patch)
treecc5c4bbc0e378c82556c8929d8ed8ce0a205be3a /drivers/gpu/drm/i915
parentd52fea5bede33818def6af692644e5de27bfc1b3 (diff)
drm/i915: Remove useless checks from primary enable/disable
We won't be calling intel_enable_primary_plane() or intel_disable_primary_plane() with the primary plane in the wrong state. So remove the useless DISPLAY_PLANE_ENABLE checks. v2: Convert the checks to WARNs instead (Daniel,Paulo) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 53746fb3c54a..72b5c34d8ce7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1887,8 +1887,7 @@ static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
1887 1887
1888 reg = DSPCNTR(plane); 1888 reg = DSPCNTR(plane);
1889 val = I915_READ(reg); 1889 val = I915_READ(reg);
1890 if (val & DISPLAY_PLANE_ENABLE) 1890 WARN_ON(val & DISPLAY_PLANE_ENABLE);
1891 return;
1892 1891
1893 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); 1892 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1894 intel_flush_primary_plane(dev_priv, plane); 1893 intel_flush_primary_plane(dev_priv, plane);
@@ -1918,8 +1917,7 @@ static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
1918 1917
1919 reg = DSPCNTR(plane); 1918 reg = DSPCNTR(plane);
1920 val = I915_READ(reg); 1919 val = I915_READ(reg);
1921 if ((val & DISPLAY_PLANE_ENABLE) == 0) 1920 WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
1922 return;
1923 1921
1924 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); 1922 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1925 intel_flush_primary_plane(dev_priv, plane); 1923 intel_flush_primary_plane(dev_priv, plane);