Merge tag 'drm-intel-next-2015-02-27' of git://anongit.freedesktop.org/drm-intel into drm-next

- Y tiling support for scanout from Tvrtko&Damien
- Remove more UMS support
- some small prep patches for OLR removal from John Harrison
- first few patches for dynamic pagetable allocation from Ben Widawsky, rebased
  by tons of other people
- DRRS support patches (Sonika&Vandana)
- fbc patches from Paulo
- make sure our vblank callbacks aren't called when the pipes are off
- various patches all over

* tag 'drm-intel-next-2015-02-27' of git://anongit.freedesktop.org/drm-intel: (61 commits)
  drm/i915: Update DRIVER_DATE to 20150227
  drm/i915: Clarify obj->map_and_fenceable
  drm/i915/skl: Allow Y (and Yf) frame buffer creation
  drm/i915/skl: Update watermarks for Y tiling
  drm/i915/skl: Updated watermark programming
  drm/i915/skl: Adjust get_plane_config() to support Yb/Yf tiling
  drm/i915/skl: Teach pin_and_fence_fb_obj() about Y tiling constraints
  drm/i915/skl: Adjust intel_fb_align_height() for Yb/Yf tiling
  drm/i915/skl: Allow scanning out Y and Yf fbs
  drm/i915/skl: Add new displayable tiling formats
  drm/i915: Remove DRIVER_MODESET checks from modeset code
  drm/i915: Remove regfile code&data for UMS suspend/resume
  drm/i915: Remove DRIVER_MODESET checks from gem code
  drm/i915: Remove DRIVER_MODESET checks in the gpu reset code
  drm/i915: Remove DRIVER_MODESET checks from suspend/resume code
  drm/i915: Remove DRIVER_MODESET checks in load/unload/close code
  drm/i915: fix a printk format
  drm/i915: Add media rc6 residency file to sysfs
  drm/i915: Add missing description to parameter in alloc_pt_range
  drm/i915: Removed the read of RP_STATE_CAP from sysfs/debugfs functions
  ...

1 files changed, 73 insertions, 16 deletions

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index d17e76d32e03..cd79c3843452 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1002,11 +1002,62 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
         return 0;
 }
 
+static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
+{
+        struct drm_device *dev = ring->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u8 vals[3] = { 0, 0, 0 };
+        unsigned int i;
+
+        for (i = 0; i < 3; i++) {
+                u8 ss;
+
+                /*
+                 * Only consider slices where one, and only one, subslice has 7
+                 * EUs
+                 */
+                if (hweight8(dev_priv->info.subslice_7eu[i]) != 1)
+                        continue;
+
+                /*
+                 * subslice_7eu[i] != 0 (because of the check above) and
+                 * ss_max == 4 (maximum number of subslices possible per slice)
+                 *
+                 * ->    0 <= ss <= 3;
+                 */
+                ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
+                vals[i] = 3 - ss;
+        }
+
+        if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
+                return 0;
+
+        /* Tune IZ hashing. See intel_device_info_runtime_init() */
+        WA_SET_FIELD_MASKED(GEN7_GT_MODE,
+                            GEN9_IZ_HASHING_MASK(2) |
+                            GEN9_IZ_HASHING_MASK(1) |
+                            GEN9_IZ_HASHING_MASK(0),
+                            GEN9_IZ_HASHING(2, vals[2]) |
+                            GEN9_IZ_HASHING(1, vals[1]) |
+                            GEN9_IZ_HASHING(0, vals[0]));
+
+        return 0;
+}
+
+
 static int skl_init_workarounds(struct intel_engine_cs *ring)
 {
+        struct drm_device *dev = ring->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
         gen9_init_workarounds(ring);
 
-        return 0;
+        /* WaDisablePowerCompilerClockGating:skl */
+        if (INTEL_REVID(dev) == SKL_REVID_B0)
+                WA_SET_BIT_MASKED(HIZ_CHICKEN,
+                                  BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
+
+        return skl_tune_iz_hashing(ring);
 }
 
 int init_workarounds_ring(struct intel_engine_cs *ring)
@@ -1690,7 +1741,7 @@ gen8_ring_put_irq(struct intel_engine_cs *ring)
 static int
 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
                          u64 offset, u32 length,
-                         unsigned flags)
+                         unsigned dispatch_flags)
 {
         int ret;
 
@@ -1701,7 +1752,8 @@ i965_dispatch_execbuffer(struct intel_engine_cs *ring,
         intel_ring_emit(ring,
                         MI_BATCH_BUFFER_START |
                         MI_BATCH_GTT |
-                        (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
+                        (dispatch_flags & I915_DISPATCH_SECURE ?
+                         0 : MI_BATCH_NON_SECURE_I965));
         intel_ring_emit(ring, offset);
         intel_ring_advance(ring);
 
@@ -1714,8 +1766,8 @@ i965_dispatch_execbuffer(struct intel_engine_cs *ring,
 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
 static int
 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
-                                u64 offset, u32 len,
-                                unsigned flags)
+                         u64 offset, u32 len,
+                         unsigned dispatch_flags)
 {
         u32 cs_offset = ring->scratch.gtt_offset;
         int ret;
@@ -1733,7 +1785,7 @@ i830_dispatch_execbuffer(struct intel_engine_cs *ring,
         intel_ring_emit(ring, MI_NOOP);
         intel_ring_advance(ring);
 
-        if ((flags & I915_DISPATCH_PINNED) == 0) {
+        if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
                 if (len > I830_BATCH_LIMIT)
                         return -ENOSPC;
 
@@ -1765,7 +1817,8 @@ i830_dispatch_execbuffer(struct intel_engine_cs *ring,
                 return ret;
 
         intel_ring_emit(ring, MI_BATCH_BUFFER);
-        intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
+        intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
+                                        0 : MI_BATCH_NON_SECURE));
         intel_ring_emit(ring, offset + len - 8);
         intel_ring_emit(ring, MI_NOOP);
         intel_ring_advance(ring);
@@ -1776,7 +1829,7 @@ i830_dispatch_execbuffer(struct intel_engine_cs *ring,
 static int
 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
                          u64 offset, u32 len,
-                         unsigned flags)
+                         unsigned dispatch_flags)
 {
         int ret;
 
@@ -1785,7 +1838,8 @@ i915_dispatch_execbuffer(struct intel_engine_cs *ring,
                 return ret;
 
         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
-        intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
+        intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
+                                        0 : MI_BATCH_NON_SECURE));
         intel_ring_advance(ring);
 
         return 0;
@@ -2176,6 +2230,7 @@ intel_ring_alloc_request(struct intel_engine_cs *ring)
 
         kref_init(&request->ref);
         request->ring = ring;
+        request->ringbuf = ring->buffer;
         request->uniq = dev_private->request_uniq++;
 
         ret = i915_gem_get_seqno(ring->dev, &request->seqno);
@@ -2352,9 +2407,10 @@ static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
 static int
 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
                               u64 offset, u32 len,
-                              unsigned flags)
+                              unsigned dispatch_flags)
 {
-        bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
+        bool ppgtt = USES_PPGTT(ring->dev) &&
+                        !(dispatch_flags & I915_DISPATCH_SECURE);
         int ret;
 
         ret = intel_ring_begin(ring, 4);
@@ -2373,8 +2429,8 @@ gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
 
 static int
 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
-                              u64 offset, u32 len,
-                              unsigned flags)
+                             u64 offset, u32 len,
+                             unsigned dispatch_flags)
 {
         int ret;
 
@@ -2384,7 +2440,7 @@ hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
 
         intel_ring_emit(ring,
                         MI_BATCH_BUFFER_START |
-                        (flags & I915_DISPATCH_SECURE ?
+                        (dispatch_flags & I915_DISPATCH_SECURE ?
                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
         /* bit0-7 is the length on GEN6+ */
         intel_ring_emit(ring, offset);
@@ -2396,7 +2452,7 @@ hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
 static int
 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
                               u64 offset, u32 len,
-                              unsigned flags)
+                              unsigned dispatch_flags)
 {
         int ret;
 
@@ -2406,7 +2462,8 @@ gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
 
         intel_ring_emit(ring,
                         MI_BATCH_BUFFER_START |
-                        (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
+                        (dispatch_flags & I915_DISPATCH_SECURE ?
+                         0 : MI_BATCH_NON_SECURE_I965));
         /* bit0-7 is the length on GEN6+ */
         intel_ring_emit(ring, offset);
         intel_ring_advance(ring);