Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
 "Intel, radeon and exynos fixes.  Nothing too major or wierd: one dmar
  fix and a radeon cursor corruption, along with misc exynos fixes."

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (21 commits)
  drm/exynos: add check for the device power status
  drm/exynos: Make 'drm_hdmi_get_edid' static
  drm/exynos: fimd and ipp are broken on multiplatform
  drm/exynos: don't include plat/gpio-cfg.h
  drm/exynos: Remove "internal" interrupt handling
  drm/exynos: Add missing static specifiers in exynos_drm_rotator.c
  drm/exynos: Replace mdelay with usleep_range
  drm/exynos: Make ipp_handle_cmd_work static
  drm/exynos: Make g2d_userptr_get_dma_addr static
  drm/exynos: consider DMA_NONE flag to dmabuf import
  drm/exynos: free sg object if dma_map_sg is failed
  drm/exynos: added validation of edid for vidi connection
  drm/exynos: let drm handle edid allocations
  drm/radeon: Enable DMA_IB_SWAP_ENABLE on big endian hosts.
  drm/radeon: fix a rare case of double kfree
  radeon_display: Use pointer return error codes
  drm/radeon: fix cursor corruption on DCE6 and newer
  drm/i915: dump UTS_RELEASE into the error_state
  iommu/intel: disable DMAR for g4x integrated gfx
  drm/i915: GFX_MODE Flush TLB Invalidate Mode must be '1' for scanline waits
  ...

1 files changed, 18 insertions, 6 deletions

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ae253e04c391..42ff97d667d2 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -505,13 +505,25 @@ static int init_render_ring(struct intel_ring_buffer *ring)
         struct drm_i915_private *dev_priv = dev->dev_private;
         int ret = init_ring_common(ring);
 
-        if (INTEL_INFO(dev)->gen > 3) {
+        if (INTEL_INFO(dev)->gen > 3)
                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
-                if (IS_GEN7(dev))
-                        I915_WRITE(GFX_MODE_GEN7,
-                                   _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
-                                   _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
-        }
+
+        /* We need to disable the AsyncFlip performance optimisations in order
+         * to use MI_WAIT_FOR_EVENT within the CS. It should already be
+         * programmed to '1' on all products.
+         */
+        if (INTEL_INFO(dev)->gen >= 6)
+                I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
+
+        /* Required for the hardware to program scanline values for waiting */
+        if (INTEL_INFO(dev)->gen == 6)
+                I915_WRITE(GFX_MODE,
+                           _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
+
+        if (IS_GEN7(dev))
+                I915_WRITE(GFX_MODE_GEN7,
+                           _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
+                           _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 
         if (INTEL_INFO(dev)->gen >= 5) {
                 ret = init_pipe_control(ring);