diff options
author | David S. Miller <davem@davemloft.net> | 2013-10-23 16:28:39 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2013-10-23 16:49:34 -0400 |
commit | c3fa32b9764dc45dcf8a2231b1c110abc4a63e0b (patch) | |
tree | 6cf2896a77b65bec64284681e1c3851eb3263e09 /drivers/gpu/drm/i915/intel_pm.c | |
parent | 34d92d5315b64a3e5292b7e9511c1bb617227fb6 (diff) | |
parent | 320437af954cbe66478f1f5e8b34cb5a8d072191 (diff) |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Conflicts:
drivers/net/usb/qmi_wwan.c
include/net/dst.h
Trivial merge conflicts, both were overlapping changes.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index dd176b7296c1..26c2ea3e985c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c | |||
@@ -3864,8 +3864,6 @@ static void valleyview_enable_rps(struct drm_device *dev) | |||
3864 | dev_priv->rps.rpe_delay), | 3864 | dev_priv->rps.rpe_delay), |
3865 | dev_priv->rps.rpe_delay); | 3865 | dev_priv->rps.rpe_delay); |
3866 | 3866 | ||
3867 | INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work); | ||
3868 | |||
3869 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay); | 3867 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay); |
3870 | 3868 | ||
3871 | gen6_enable_rps_interrupts(dev); | 3869 | gen6_enable_rps_interrupts(dev); |
@@ -4761,7 +4759,9 @@ static void cpt_init_clock_gating(struct drm_device *dev) | |||
4761 | * gating for the panel power sequencer or it will fail to | 4759 | * gating for the panel power sequencer or it will fail to |
4762 | * start up when no ports are active. | 4760 | * start up when no ports are active. |
4763 | */ | 4761 | */ |
4764 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | 4762 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | |
4763 | PCH_DPLUNIT_CLOCK_GATE_DISABLE | | ||
4764 | PCH_CPUNIT_CLOCK_GATE_DISABLE); | ||
4765 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | | 4765 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
4766 | DPLS_EDP_PPS_FIX_DIS); | 4766 | DPLS_EDP_PPS_FIX_DIS); |
4767 | /* The below fixes the weird display corruption, a few pixels shifted | 4767 | /* The below fixes the weird display corruption, a few pixels shifted |
@@ -4955,6 +4955,11 @@ static void haswell_init_clock_gating(struct drm_device *dev) | |||
4955 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, | 4955 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, |
4956 | GEN7_WA_L3_CHICKEN_MODE); | 4956 | GEN7_WA_L3_CHICKEN_MODE); |
4957 | 4957 | ||
4958 | /* L3 caching of data atomics doesn't work -- disable it. */ | ||
4959 | I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); | ||
4960 | I915_WRITE(HSW_ROW_CHICKEN3, | ||
4961 | _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); | ||
4962 | |||
4958 | /* This is required by WaCatErrorRejectionIssue:hsw */ | 4963 | /* This is required by WaCatErrorRejectionIssue:hsw */ |
4959 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, | 4964 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
4960 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | 4965 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
@@ -5681,5 +5686,7 @@ void intel_pm_init(struct drm_device *dev) | |||
5681 | 5686 | ||
5682 | INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, | 5687 | INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, |
5683 | intel_gen6_powersave_work); | 5688 | intel_gen6_powersave_work); |
5689 | |||
5690 | INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work); | ||
5684 | } | 5691 | } |
5685 | 5692 | ||