diff options
author | Ben Widawsky <benjamin.widawsky@intel.com> | 2013-10-24 12:59:11 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-10-27 09:43:10 -0400 |
commit | a74b0c481589762f28f35a26b2c77126f38de652 (patch) | |
tree | e8982593877eeca24b312b6850b8f245251eeb0d /drivers/gpu/drm/i915/intel_pm.c | |
parent | 153b4b9547965729120d427485e414855399acac (diff) |
drm/i915: Remove WaFbcDisableDpfcClockGating on IVB
Production IVB does not need it. I confirmed this with Art.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2f26d6c2fc93..c325a57b89b5 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c | |||
@@ -254,12 +254,6 @@ static void ironlake_disable_fbc(struct drm_device *dev) | |||
254 | dpfc_ctl &= ~DPFC_CTL_EN; | 254 | dpfc_ctl &= ~DPFC_CTL_EN; |
255 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | 255 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); |
256 | 256 | ||
257 | if (IS_IVYBRIDGE(dev)) | ||
258 | /* WaFbcDisableDpfcClockGating:ivb */ | ||
259 | I915_WRITE(ILK_DSPCLK_GATE_D, | ||
260 | I915_READ(ILK_DSPCLK_GATE_D) & | ||
261 | ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE); | ||
262 | |||
263 | if (IS_HASWELL(dev)) | 257 | if (IS_HASWELL(dev)) |
264 | /* WaFbcDisableDpfcClockGating:hsw */ | 258 | /* WaFbcDisableDpfcClockGating:hsw */ |
265 | I915_WRITE(HSW_CLKGATE_DISABLE_PART_1, | 259 | I915_WRITE(HSW_CLKGATE_DISABLE_PART_1, |
@@ -295,10 +289,6 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | |||
295 | if (IS_IVYBRIDGE(dev)) { | 289 | if (IS_IVYBRIDGE(dev)) { |
296 | /* WaFbcAsynchFlipDisableFbcQueue:ivb */ | 290 | /* WaFbcAsynchFlipDisableFbcQueue:ivb */ |
297 | I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS); | 291 | I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS); |
298 | /* WaFbcDisableDpfcClockGating:ivb */ | ||
299 | I915_WRITE(ILK_DSPCLK_GATE_D, | ||
300 | I915_READ(ILK_DSPCLK_GATE_D) | | ||
301 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE); | ||
302 | } else { | 292 | } else { |
303 | /* WaFbcAsynchFlipDisableFbcQueue:hsw */ | 293 | /* WaFbcAsynchFlipDisableFbcQueue:hsw */ |
304 | I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe), | 294 | I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe), |