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authorLinus Torvalds <torvalds@linux-foundation.org>2012-08-14 00:52:41 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-08-14 00:52:41 -0400
commit930a93a5ef69ee06057e3ccd8c90b23e98ad3c11 (patch)
tree632398de05daf76d1c3fdc1e58dc6127b841d312 /drivers/gpu/drm/i915/intel_pm.c
parentf43e04ec46b67071d432fc3f368dc9891a3443e5 (diff)
parent7bac6b46607f2f44075cb45dd5b0b4d2e7c80695 (diff)
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "Radeon and intel fixes mostly, one fix to the mgag200 driver to not hang on certain server variants." * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (32 commits) drm/radeon: fix typo in function header comment drm/radeon/kms: implement timestamp userspace query (v2) drm/radeon/kms: add MSAA texture support for r600-evergreen drm/radeon/kms: reorder code in r600_check_texture_resource drm/radeon: fence virtual address and free it once idle v4 drm/radeon: fix some missing parens in asic macros drm/radeon: add some new SI pci ids drm/radeon: fix ordering in pll picking on dce4+ drm/radeon: do not reenable crtc after moving vram start address drm/radeon: fix bank tiling parameters on cayman drm/radeon: fix bank tiling parameters on evergreen drm/radeon: fix bank tiling parameters on SI drm/radeon: properly handle crtc powergating drm/radeon: properly handle SS overrides on TN (v2) drm/radeon/dce4+: set a more reasonable cursor watermark drm/radeon: fix handling for ddc type 5 on combios drm/mgag200: fix G200ER pll picking algorithm drm/edid: Fix potential memory leak in edid_load() drm/udl: Use ERR_CAST inlined function instead of ERR_PTR(PTR_ERR(.. [1] drm/radeon/kms: allow "invalid" DB formats as a means to disable DB ...
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 94aabcaa3a67..58c07cdafb7e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3963,6 +3963,7 @@ static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
3963 DRM_ERROR("Force wake wait timed out\n"); 3963 DRM_ERROR("Force wake wait timed out\n");
3964 3964
3965 I915_WRITE_NOTRACE(FORCEWAKE, 1); 3965 I915_WRITE_NOTRACE(FORCEWAKE, 1);
3966 POSTING_READ(FORCEWAKE);
3966 3967
3967 if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500)) 3968 if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500))
3968 DRM_ERROR("Force wake wait timed out\n"); 3969 DRM_ERROR("Force wake wait timed out\n");
@@ -3983,6 +3984,7 @@ static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
3983 DRM_ERROR("Force wake wait timed out\n"); 3984 DRM_ERROR("Force wake wait timed out\n");
3984 3985
3985 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1)); 3986 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
3987 POSTING_READ(FORCEWAKE_MT);
3986 3988
3987 if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500)) 3989 if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500))
3988 DRM_ERROR("Force wake wait timed out\n"); 3990 DRM_ERROR("Force wake wait timed out\n");
@@ -4018,14 +4020,14 @@ void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4018static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) 4020static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4019{ 4021{
4020 I915_WRITE_NOTRACE(FORCEWAKE, 0); 4022 I915_WRITE_NOTRACE(FORCEWAKE, 0);
4021 /* The below doubles as a POSTING_READ */ 4023 POSTING_READ(FORCEWAKE);
4022 gen6_gt_check_fifodbg(dev_priv); 4024 gen6_gt_check_fifodbg(dev_priv);
4023} 4025}
4024 4026
4025static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) 4027static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4026{ 4028{
4027 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1)); 4029 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));
4028 /* The below doubles as a POSTING_READ */ 4030 POSTING_READ(FORCEWAKE_MT);
4029 gen6_gt_check_fifodbg(dev_priv); 4031 gen6_gt_check_fifodbg(dev_priv);
4030} 4032}
4031 4033