Merge tag 'drm-intel-next-2014-07-11' of git://anongit.freedesktop.org/drm-intel into drm-next

- fbc improvements when stolen memory is tight (Ben)
- cdclk handling improvements for vlv/chv (Ville)
- proper fix for stuck primary planes on gmch platforms with cxsr (Imre&Ebgert
  Eich)
- gen8 hw semaphore support (Ben)
- more execlist prep work from Oscar Mateo
- locking fixes for primary planes (Matt Roper)
- code rework to support runtime pm for dpms on hsw/bdw (Paulo, Imre & me), but
  not yet enabled because some fixes from Paulo haven't made the cut
- more gpu boost tuning from Chris
- as usual piles of little things all over

* tag 'drm-intel-next-2014-07-11' of git://anongit.freedesktop.org/drm-intel: (93 commits)
  drm/i915: Make the RPS interrupt generation mask handle the vlv wa
  drm/i915: Move RPS evaluation interval counters to i915->rps
  drm/i915: Don't cast a pointer to void* unnecessarily
  drm/i915: don't read LVDS regs at compute_config time
  drm/i915: check the power domains in intel_lvds_get_hw_state()
  drm/i915: check the power domains in ironlake_get_pipe_config()
  drm/i915: don't skip shared DPLL assertion on LPT
  drm/i915: Only touch WRPLL hw state in enable/disable hooks
  drm/i915: Switch to common shared dpll framework for WRPLLs
  drm/i915: ->enable hook for WRPLLs
  drm/i915: ->disable hook for WRPLLs
  drm/i915: State readout support for WRPLLs
  drm/i915: add POWER_DOMAIN_PLLS
  drm/i915: Document that the pll->mode_set hook is optional
  drm/i915: Basic shared dpll support for WRPLLs
  drm/i915: Precompute static ddi_pll_sel values in encoders
  drm/i915: BDW also has special-purpose DP DDI clocks
  drm/i915: State readout and cross-checking for ddi_pll_sel
  drm/i915: Move ddi_pll_sel into the pipe config
  drm/i915: Add a debugfs file for the shared dpll state
  ...

1 files changed, 14 insertions, 4 deletions

diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 4d29a83fd163..c511287bbb86 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -51,6 +51,7 @@ struct intel_lvds_encoder {
 
         bool is_dual_link;
         u32 reg;
+        u32 a3_power;
 
         struct intel_lvds_connector *attached_connector;
 };
@@ -71,8 +72,13 @@ static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
         struct drm_device *dev = encoder->base.dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
+        enum intel_display_power_domain power_domain;
         u32 tmp;
 
+        power_domain = intel_display_port_power_domain(encoder);
+        if (!intel_display_power_enabled(dev_priv, power_domain))
+                return false;
+
         tmp = I915_READ(lvds_encoder->reg);
 
         if (!(tmp & LVDS_PORT_EN))
@@ -165,8 +171,11 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder)
 
         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
          * appropriately here, but we need to look more thoroughly into how
-         * panels behave in the two modes.
+         * panels behave in the two modes. For now, let's just maintain the
+         * value we got from the BIOS.
          */
+         temp &= ~LVDS_A3_POWER_MASK;
+         temp |= lvds_encoder->a3_power;
 
         /* Set the dithering flag on LVDS as needed, note that there is no
          * special lvds dither control bit on pch-split platforms, dithering is
@@ -264,7 +273,6 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
                                       struct intel_crtc_config *pipe_config)
 {
         struct drm_device *dev = intel_encoder->base.dev;
-        struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_lvds_encoder *lvds_encoder =
                 to_lvds_encoder(&intel_encoder->base);
         struct intel_connector *intel_connector =
@@ -279,8 +287,7 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
                 return false;
         }
 
-        if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) ==
-            LVDS_A3_POWER_UP)
+        if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
                 lvds_bpp = 8*3;
         else
                 lvds_bpp = 6*3;
@@ -1081,6 +1088,9 @@ out:
         DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
                       lvds_encoder->is_dual_link ? "dual" : "single");
 
+        lvds_encoder->a3_power = I915_READ(lvds_encoder->reg) &
+                                 LVDS_A3_POWER_MASK;
+
         /*
          * Unlock registers and just
          * leave them unlocked