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authorChris Wilson <chris@chris-wilson.co.uk>2010-09-21 09:06:12 -0400
committerChris Wilson <chris@chris-wilson.co.uk>2010-09-21 09:22:54 -0400
commit4fd21dc8ee6fde52a99042186ff94de1b5e8b43c (patch)
tree4fcc7d1a8a9754879709ca123497d3f324b1900c /drivers/gpu/drm/i915/intel_lvds.c
parenta6b17b4367ed5d9bac94bc87d1489de3847fce98 (diff)
drm/i915/lvds: Unlock the PP register when panel-fitting
As we do not wait for the panel to turn off when we need to adjust the panel-fitting registers we also need to unlock the PLLs as with the non-pfit update path. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_lvds.c')
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 02c5aed36c87..2bcea8000859 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -97,6 +97,7 @@ static void intel_lvds_set_power(struct intel_lvds *intel_lvds, bool on)
97 DRM_ERROR("timed out waiting for panel to power off\n"); 97 DRM_ERROR("timed out waiting for panel to power off\n");
98 I915_WRITE(PFIT_CONTROL, 0); 98 I915_WRITE(PFIT_CONTROL, 0);
99 intel_lvds->pfit_control = 0; 99 intel_lvds->pfit_control = 0;
100 intel_lvds->pfit_dirty = false;
100 } 101 }
101 102
102 I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN); 103 I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN);
@@ -377,8 +378,8 @@ static void intel_lvds_prepare(struct drm_encoder *encoder)
377 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); 378 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
378 } else if (intel_lvds->pfit_dirty) { 379 } else if (intel_lvds->pfit_dirty) {
379 I915_WRITE(PP_CONTROL, 380 I915_WRITE(PP_CONTROL,
380 I915_READ(PP_CONTROL) & ~POWER_TARGET_ON); 381 (I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS)
381 I915_WRITE(LVDS, I915_READ(LVDS) & ~LVDS_PORT_EN); 382 & ~POWER_TARGET_ON);
382 } else { 383 } else {
383 I915_WRITE(PP_CONTROL, 384 I915_WRITE(PP_CONTROL,
384 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); 385 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
@@ -438,6 +439,9 @@ static void intel_lvds_mode_set(struct drm_encoder *encoder,
438 * screen. Should be enabled before the pipe is enabled, according to 439 * screen. Should be enabled before the pipe is enabled, according to
439 * register description and PRM. 440 * register description and PRM.
440 */ 441 */
442 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
443 intel_lvds->pfit_control,
444 intel_lvds->pfit_pgm_ratios);
441 if (wait_for((I915_READ(PP_STATUS) & PP_ON) == 0, 1000)) 445 if (wait_for((I915_READ(PP_STATUS) & PP_ON) == 0, 1000))
442 DRM_ERROR("timed out waiting for panel to power off\n"); 446 DRM_ERROR("timed out waiting for panel to power off\n");
443 447