diff options
author | Jani Nikula <jani.nikula@intel.com> | 2013-05-22 08:36:18 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-05-23 17:24:46 -0400 |
commit | a1ca802d98acbc5fd87cc399b6aaf38f54be33e1 (patch) | |
tree | 82f4475420912a6842b26388c251700b41a60615 /drivers/gpu/drm/i915/intel_hdmi.c | |
parent | 5a09ae9fd509d7dded34e0d599e1afa5142c6987 (diff) |
drm/i915: drop redundant warnings on not holding dpio_lock
The lower level sideband read/write functions already do this.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_hdmi.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_hdmi.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 18f8ce0404c6..83b63d72af83 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c | |||
@@ -1018,8 +1018,6 @@ static void intel_hdmi_pre_enable(struct intel_encoder *encoder) | |||
1018 | if (!IS_VALLEYVIEW(dev)) | 1018 | if (!IS_VALLEYVIEW(dev)) |
1019 | return; | 1019 | return; |
1020 | 1020 | ||
1021 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); | ||
1022 | |||
1023 | /* Enable clock channels for this port */ | 1021 | /* Enable clock channels for this port */ |
1024 | val = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(port)); | 1022 | val = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(port)); |
1025 | val = 0; | 1023 | val = 0; |
@@ -1063,8 +1061,6 @@ static void intel_hdmi_pre_pll_enable(struct intel_encoder *encoder) | |||
1063 | if (!IS_VALLEYVIEW(dev)) | 1061 | if (!IS_VALLEYVIEW(dev)) |
1064 | return; | 1062 | return; |
1065 | 1063 | ||
1066 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); | ||
1067 | |||
1068 | /* Program Tx lane resets to default */ | 1064 | /* Program Tx lane resets to default */ |
1069 | intel_dpio_write(dev_priv, DPIO_PCS_TX(port), | 1065 | intel_dpio_write(dev_priv, DPIO_PCS_TX(port), |
1070 | DPIO_PCS_TX_LANE2_RESET | | 1066 | DPIO_PCS_TX_LANE2_RESET | |