drm/i915: set the correct eDP aux channel clock divider on DDI

The cdclk frequency is not always the same, so the value here should
be adjusted to match it.

Version 2: call intel_ddi_get_cdclk_freq instead of reading
CDCLK_FREQ, because the register is just for earlier HW steppings.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 3 insertions, 1 deletions

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7e3c1deb80b1..8c9bbc2f456b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -370,7 +370,9 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
          * clock divider.
          */
         if (is_cpu_edp(intel_dp)) {
-                if (IS_VALLEYVIEW(dev))
+                if (IS_HASWELL(dev))
+                        aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
+                else if (IS_VALLEYVIEW(dev))
                         aux_clock_divider = 100;
                 else if (IS_GEN6(dev) || IS_GEN7(dev))
                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */