diff options
author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-03-19 10:54:37 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-03-19 10:54:37 -0400 |
commit | b80d6c781e7eb16e24c2a04a88ab6b230bcbbb35 (patch) | |
tree | aeb0885a6a3499ef96b2472be323965db8e1295e /drivers/gpu/drm/i915/intel_dp.c | |
parent | 262ca2b08fbdb9346e66ef30424b2226a00e0ffc (diff) | |
parent | 0b99836f238f37a8632a3ab4f9a8cc2346a36d40 (diff) |
Merge branch 'topic/dp-aux-rework' into drm-intel-next-queued
Conflicts:
drivers/gpu/drm/i915/intel_dp.c
A bit a mess with reverts which differe in details between -fixes and
-next and some other unrelated shuffling.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 513 |
1 files changed, 182 insertions, 331 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index fb8a967df027..bbb1327644d4 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c | |||
@@ -91,6 +91,7 @@ static struct intel_dp *intel_attached_dp(struct drm_connector *connector) | |||
91 | } | 91 | } |
92 | 92 | ||
93 | static void intel_dp_link_down(struct intel_dp *intel_dp); | 93 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
94 | static bool _edp_panel_vdd_on(struct intel_dp *intel_dp); | ||
94 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); | 95 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
95 | 96 | ||
96 | static int | 97 | static int |
@@ -459,6 +460,9 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, | |||
459 | uint32_t status; | 460 | uint32_t status; |
460 | int try, clock = 0; | 461 | int try, clock = 0; |
461 | bool has_aux_irq = HAS_AUX_IRQ(dev); | 462 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
463 | bool vdd; | ||
464 | |||
465 | vdd = _edp_panel_vdd_on(intel_dp); | ||
462 | 466 | ||
463 | /* dp aux is extremely sensitive to irq latency, hence request the | 467 | /* dp aux is extremely sensitive to irq latency, hence request the |
464 | * lowest possible wakeup latency and so prevent the cpu from going into | 468 | * lowest possible wakeup latency and so prevent the cpu from going into |
@@ -564,223 +568,130 @@ out: | |||
564 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); | 568 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); |
565 | intel_aux_display_runtime_put(dev_priv); | 569 | intel_aux_display_runtime_put(dev_priv); |
566 | 570 | ||
571 | if (vdd) | ||
572 | edp_panel_vdd_off(intel_dp, false); | ||
573 | |||
567 | return ret; | 574 | return ret; |
568 | } | 575 | } |
569 | 576 | ||
570 | /* Write data to the aux channel in native mode */ | 577 | #define HEADER_SIZE 4 |
571 | static int | 578 | static ssize_t |
572 | intel_dp_aux_native_write(struct intel_dp *intel_dp, | 579 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
573 | uint16_t address, uint8_t *send, int send_bytes) | ||
574 | { | 580 | { |
581 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); | ||
582 | uint8_t txbuf[20], rxbuf[20]; | ||
583 | size_t txsize, rxsize; | ||
575 | int ret; | 584 | int ret; |
576 | uint8_t msg[20]; | ||
577 | int msg_bytes; | ||
578 | uint8_t ack; | ||
579 | int retry; | ||
580 | 585 | ||
581 | if (WARN_ON(send_bytes > 16)) | 586 | txbuf[0] = msg->request << 4; |
582 | return -E2BIG; | 587 | txbuf[1] = msg->address >> 8; |
588 | txbuf[2] = msg->address & 0xff; | ||
589 | txbuf[3] = msg->size - 1; | ||
583 | 590 | ||
584 | intel_dp_check_edp(intel_dp); | 591 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
585 | msg[0] = DP_AUX_NATIVE_WRITE << 4; | 592 | case DP_AUX_NATIVE_WRITE: |
586 | msg[1] = address >> 8; | 593 | case DP_AUX_I2C_WRITE: |
587 | msg[2] = address & 0xff; | 594 | txsize = HEADER_SIZE + msg->size; |
588 | msg[3] = send_bytes - 1; | 595 | rxsize = 1; |
589 | memcpy(&msg[4], send, send_bytes); | ||
590 | msg_bytes = send_bytes + 4; | ||
591 | for (retry = 0; retry < 7; retry++) { | ||
592 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); | ||
593 | if (ret < 0) | ||
594 | return ret; | ||
595 | ack >>= 4; | ||
596 | if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) | ||
597 | return send_bytes; | ||
598 | else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) | ||
599 | usleep_range(400, 500); | ||
600 | else | ||
601 | return -EIO; | ||
602 | } | ||
603 | 596 | ||
604 | DRM_ERROR("too many retries, giving up\n"); | 597 | if (WARN_ON(txsize > 20)) |
605 | return -EIO; | 598 | return -E2BIG; |
606 | } | ||
607 | 599 | ||
608 | /* Write a single byte to the aux channel in native mode */ | 600 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); |
609 | static int | ||
610 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, | ||
611 | uint16_t address, uint8_t byte) | ||
612 | { | ||
613 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); | ||
614 | } | ||
615 | 601 | ||
616 | /* read bytes from a native aux channel */ | 602 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
617 | static int | 603 | if (ret > 0) { |
618 | intel_dp_aux_native_read(struct intel_dp *intel_dp, | 604 | msg->reply = rxbuf[0] >> 4; |
619 | uint16_t address, uint8_t *recv, int recv_bytes) | ||
620 | { | ||
621 | uint8_t msg[4]; | ||
622 | int msg_bytes; | ||
623 | uint8_t reply[20]; | ||
624 | int reply_bytes; | ||
625 | uint8_t ack; | ||
626 | int ret; | ||
627 | int retry; | ||
628 | 605 | ||
629 | if (WARN_ON(recv_bytes > 19)) | 606 | /* Return payload size. */ |
630 | return -E2BIG; | 607 | ret = msg->size; |
608 | } | ||
609 | break; | ||
631 | 610 | ||
632 | intel_dp_check_edp(intel_dp); | 611 | case DP_AUX_NATIVE_READ: |
633 | msg[0] = DP_AUX_NATIVE_READ << 4; | 612 | case DP_AUX_I2C_READ: |
634 | msg[1] = address >> 8; | 613 | txsize = HEADER_SIZE; |
635 | msg[2] = address & 0xff; | 614 | rxsize = msg->size + 1; |
636 | msg[3] = recv_bytes - 1; | 615 | |
637 | 616 | if (WARN_ON(rxsize > 20)) | |
638 | msg_bytes = 4; | 617 | return -E2BIG; |
639 | reply_bytes = recv_bytes + 1; | 618 | |
640 | 619 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); | |
641 | for (retry = 0; retry < 7; retry++) { | 620 | if (ret > 0) { |
642 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, | 621 | msg->reply = rxbuf[0] >> 4; |
643 | reply, reply_bytes); | 622 | /* |
644 | if (ret == 0) | 623 | * Assume happy day, and copy the data. The caller is |
645 | return -EPROTO; | 624 | * expected to check msg->reply before touching it. |
646 | if (ret < 0) | 625 | * |
647 | return ret; | 626 | * Return payload size. |
648 | ack = reply[0] >> 4; | 627 | */ |
649 | if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) { | 628 | ret--; |
650 | memcpy(recv, reply + 1, ret - 1); | 629 | memcpy(msg->buffer, rxbuf + 1, ret); |
651 | return ret - 1; | ||
652 | } | 630 | } |
653 | else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) | 631 | break; |
654 | usleep_range(400, 500); | 632 | |
655 | else | 633 | default: |
656 | return -EIO; | 634 | ret = -EINVAL; |
635 | break; | ||
657 | } | 636 | } |
658 | 637 | ||
659 | DRM_ERROR("too many retries, giving up\n"); | 638 | return ret; |
660 | return -EIO; | ||
661 | } | 639 | } |
662 | 640 | ||
663 | static int | 641 | static void |
664 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, | 642 | intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) |
665 | uint8_t write_byte, uint8_t *read_byte) | 643 | { |
666 | { | 644 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
667 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; | 645 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
668 | struct intel_dp *intel_dp = container_of(adapter, | 646 | enum port port = intel_dig_port->port; |
669 | struct intel_dp, | 647 | const char *name = NULL; |
670 | adapter); | ||
671 | uint16_t address = algo_data->address; | ||
672 | uint8_t msg[5]; | ||
673 | uint8_t reply[2]; | ||
674 | unsigned retry; | ||
675 | int msg_bytes; | ||
676 | int reply_bytes; | ||
677 | int ret; | 648 | int ret; |
678 | 649 | ||
679 | intel_edp_panel_vdd_on(intel_dp); | 650 | switch (port) { |
680 | intel_dp_check_edp(intel_dp); | 651 | case PORT_A: |
681 | /* Set up the command byte */ | 652 | intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; |
682 | if (mode & MODE_I2C_READ) | 653 | name = "DPDDC-A"; |
683 | msg[0] = DP_AUX_I2C_READ << 4; | ||
684 | else | ||
685 | msg[0] = DP_AUX_I2C_WRITE << 4; | ||
686 | |||
687 | if (!(mode & MODE_I2C_STOP)) | ||
688 | msg[0] |= DP_AUX_I2C_MOT << 4; | ||
689 | |||
690 | msg[1] = address >> 8; | ||
691 | msg[2] = address; | ||
692 | |||
693 | switch (mode) { | ||
694 | case MODE_I2C_WRITE: | ||
695 | msg[3] = 0; | ||
696 | msg[4] = write_byte; | ||
697 | msg_bytes = 5; | ||
698 | reply_bytes = 1; | ||
699 | break; | 654 | break; |
700 | case MODE_I2C_READ: | 655 | case PORT_B: |
701 | msg[3] = 0; | 656 | intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; |
702 | msg_bytes = 4; | 657 | name = "DPDDC-B"; |
703 | reply_bytes = 2; | ||
704 | break; | 658 | break; |
705 | default: | 659 | case PORT_C: |
706 | msg_bytes = 3; | 660 | intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; |
707 | reply_bytes = 1; | 661 | name = "DPDDC-C"; |
708 | break; | 662 | break; |
663 | case PORT_D: | ||
664 | intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; | ||
665 | name = "DPDDC-D"; | ||
666 | break; | ||
667 | default: | ||
668 | BUG(); | ||
709 | } | 669 | } |
710 | 670 | ||
711 | /* | 671 | if (!HAS_DDI(dev)) |
712 | * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is | 672 | intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; |
713 | * required to retry at least seven times upon receiving AUX_DEFER | ||
714 | * before giving up the AUX transaction. | ||
715 | */ | ||
716 | for (retry = 0; retry < 7; retry++) { | ||
717 | ret = intel_dp_aux_ch(intel_dp, | ||
718 | msg, msg_bytes, | ||
719 | reply, reply_bytes); | ||
720 | if (ret < 0) { | ||
721 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); | ||
722 | goto out; | ||
723 | } | ||
724 | 673 | ||
725 | switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) { | 674 | intel_dp->aux.name = name; |
726 | case DP_AUX_NATIVE_REPLY_ACK: | 675 | intel_dp->aux.dev = dev->dev; |
727 | /* I2C-over-AUX Reply field is only valid | 676 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
728 | * when paired with AUX ACK. | ||
729 | */ | ||
730 | break; | ||
731 | case DP_AUX_NATIVE_REPLY_NACK: | ||
732 | DRM_DEBUG_KMS("aux_ch native nack\n"); | ||
733 | ret = -EREMOTEIO; | ||
734 | goto out; | ||
735 | case DP_AUX_NATIVE_REPLY_DEFER: | ||
736 | /* | ||
737 | * For now, just give more slack to branch devices. We | ||
738 | * could check the DPCD for I2C bit rate capabilities, | ||
739 | * and if available, adjust the interval. We could also | ||
740 | * be more careful with DP-to-Legacy adapters where a | ||
741 | * long legacy cable may force very low I2C bit rates. | ||
742 | */ | ||
743 | if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | ||
744 | DP_DWN_STRM_PORT_PRESENT) | ||
745 | usleep_range(500, 600); | ||
746 | else | ||
747 | usleep_range(300, 400); | ||
748 | continue; | ||
749 | default: | ||
750 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", | ||
751 | reply[0]); | ||
752 | ret = -EREMOTEIO; | ||
753 | goto out; | ||
754 | } | ||
755 | 677 | ||
756 | switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) { | 678 | DRM_DEBUG_KMS("registering %s bus for %s\n", name, |
757 | case DP_AUX_I2C_REPLY_ACK: | 679 | connector->base.kdev->kobj.name); |
758 | if (mode == MODE_I2C_READ) { | ||
759 | *read_byte = reply[1]; | ||
760 | } | ||
761 | ret = reply_bytes - 1; | ||
762 | goto out; | ||
763 | case DP_AUX_I2C_REPLY_NACK: | ||
764 | DRM_DEBUG_KMS("aux_i2c nack\n"); | ||
765 | ret = -EREMOTEIO; | ||
766 | goto out; | ||
767 | case DP_AUX_I2C_REPLY_DEFER: | ||
768 | DRM_DEBUG_KMS("aux_i2c defer\n"); | ||
769 | udelay(100); | ||
770 | break; | ||
771 | default: | ||
772 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); | ||
773 | ret = -EREMOTEIO; | ||
774 | goto out; | ||
775 | } | ||
776 | } | ||
777 | 680 | ||
778 | DRM_ERROR("too many retries, giving up\n"); | 681 | ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux); |
779 | ret = -EREMOTEIO; | 682 | if (ret < 0) { |
683 | DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n", | ||
684 | name, ret); | ||
685 | return; | ||
686 | } | ||
780 | 687 | ||
781 | out: | 688 | ret = sysfs_create_link(&connector->base.kdev->kobj, |
782 | edp_panel_vdd_off(intel_dp, false); | 689 | &intel_dp->aux.ddc.dev.kobj, |
783 | return ret; | 690 | intel_dp->aux.ddc.dev.kobj.name); |
691 | if (ret < 0) { | ||
692 | DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret); | ||
693 | drm_dp_aux_unregister_i2c_bus(&intel_dp->aux); | ||
694 | } | ||
784 | } | 695 | } |
785 | 696 | ||
786 | static void | 697 | static void |
@@ -789,43 +700,10 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector) | |||
789 | struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); | 700 | struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); |
790 | 701 | ||
791 | sysfs_remove_link(&intel_connector->base.kdev->kobj, | 702 | sysfs_remove_link(&intel_connector->base.kdev->kobj, |
792 | intel_dp->adapter.dev.kobj.name); | 703 | intel_dp->aux.ddc.dev.kobj.name); |
793 | intel_connector_unregister(intel_connector); | 704 | intel_connector_unregister(intel_connector); |
794 | } | 705 | } |
795 | 706 | ||
796 | static int | ||
797 | intel_dp_i2c_init(struct intel_dp *intel_dp, | ||
798 | struct intel_connector *intel_connector, const char *name) | ||
799 | { | ||
800 | int ret; | ||
801 | |||
802 | DRM_DEBUG_KMS("i2c_init %s\n", name); | ||
803 | intel_dp->algo.running = false; | ||
804 | intel_dp->algo.address = 0; | ||
805 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; | ||
806 | |||
807 | memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); | ||
808 | intel_dp->adapter.owner = THIS_MODULE; | ||
809 | intel_dp->adapter.class = I2C_CLASS_DDC; | ||
810 | strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); | ||
811 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; | ||
812 | intel_dp->adapter.algo_data = &intel_dp->algo; | ||
813 | intel_dp->adapter.dev.parent = intel_connector->base.dev->dev; | ||
814 | |||
815 | ret = i2c_dp_aux_add_bus(&intel_dp->adapter); | ||
816 | if (ret < 0) | ||
817 | return ret; | ||
818 | |||
819 | ret = sysfs_create_link(&intel_connector->base.kdev->kobj, | ||
820 | &intel_dp->adapter.dev.kobj, | ||
821 | intel_dp->adapter.dev.kobj.name); | ||
822 | |||
823 | if (ret < 0) | ||
824 | i2c_del_adapter(&intel_dp->adapter); | ||
825 | |||
826 | return ret; | ||
827 | } | ||
828 | |||
829 | static void | 707 | static void |
830 | intel_dp_set_clock(struct intel_encoder *encoder, | 708 | intel_dp_set_clock(struct intel_encoder *encoder, |
831 | struct intel_crtc_config *pipe_config, int link_bw) | 709 | struct intel_crtc_config *pipe_config, int link_bw) |
@@ -1161,23 +1039,21 @@ static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) | |||
1161 | return control; | 1039 | return control; |
1162 | } | 1040 | } |
1163 | 1041 | ||
1164 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) | 1042 | static bool _edp_panel_vdd_on(struct intel_dp *intel_dp) |
1165 | { | 1043 | { |
1166 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | 1044 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1167 | struct drm_i915_private *dev_priv = dev->dev_private; | 1045 | struct drm_i915_private *dev_priv = dev->dev_private; |
1168 | u32 pp; | 1046 | u32 pp; |
1169 | u32 pp_stat_reg, pp_ctrl_reg; | 1047 | u32 pp_stat_reg, pp_ctrl_reg; |
1048 | bool need_to_disable = !intel_dp->want_panel_vdd; | ||
1170 | 1049 | ||
1171 | if (!is_edp(intel_dp)) | 1050 | if (!is_edp(intel_dp)) |
1172 | return; | 1051 | return false; |
1173 | |||
1174 | WARN(intel_dp->want_panel_vdd, | ||
1175 | "eDP VDD already requested on\n"); | ||
1176 | 1052 | ||
1177 | intel_dp->want_panel_vdd = true; | 1053 | intel_dp->want_panel_vdd = true; |
1178 | 1054 | ||
1179 | if (edp_have_panel_vdd(intel_dp)) | 1055 | if (edp_have_panel_vdd(intel_dp)) |
1180 | return; | 1056 | return need_to_disable; |
1181 | 1057 | ||
1182 | intel_runtime_pm_get(dev_priv); | 1058 | intel_runtime_pm_get(dev_priv); |
1183 | 1059 | ||
@@ -1203,6 +1079,17 @@ void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) | |||
1203 | DRM_DEBUG_KMS("eDP was not running\n"); | 1079 | DRM_DEBUG_KMS("eDP was not running\n"); |
1204 | msleep(intel_dp->panel_power_up_delay); | 1080 | msleep(intel_dp->panel_power_up_delay); |
1205 | } | 1081 | } |
1082 | |||
1083 | return need_to_disable; | ||
1084 | } | ||
1085 | |||
1086 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) | ||
1087 | { | ||
1088 | if (is_edp(intel_dp)) { | ||
1089 | bool vdd = _edp_panel_vdd_on(intel_dp); | ||
1090 | |||
1091 | WARN(!vdd, "eDP VDD already requested on\n"); | ||
1092 | } | ||
1206 | } | 1093 | } |
1207 | 1094 | ||
1208 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) | 1095 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
@@ -1465,8 +1352,8 @@ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) | |||
1465 | return; | 1352 | return; |
1466 | 1353 | ||
1467 | if (mode != DRM_MODE_DPMS_ON) { | 1354 | if (mode != DRM_MODE_DPMS_ON) { |
1468 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, | 1355 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
1469 | DP_SET_POWER_D3); | 1356 | DP_SET_POWER_D3); |
1470 | if (ret != 1) | 1357 | if (ret != 1) |
1471 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); | 1358 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); |
1472 | } else { | 1359 | } else { |
@@ -1475,9 +1362,8 @@ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) | |||
1475 | * time to wake up. | 1362 | * time to wake up. |
1476 | */ | 1363 | */ |
1477 | for (i = 0; i < 3; i++) { | 1364 | for (i = 0; i < 3; i++) { |
1478 | ret = intel_dp_aux_native_write_1(intel_dp, | 1365 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
1479 | DP_SET_POWER, | 1366 | DP_SET_POWER_D0); |
1480 | DP_SET_POWER_D0); | ||
1481 | if (ret == 1) | 1367 | if (ret == 1) |
1482 | break; | 1368 | break; |
1483 | msleep(1); | 1369 | msleep(1); |
@@ -1701,13 +1587,11 @@ static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) | |||
1701 | 1587 | ||
1702 | /* Enable PSR in sink */ | 1588 | /* Enable PSR in sink */ |
1703 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) | 1589 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) |
1704 | intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, | 1590 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, |
1705 | DP_PSR_ENABLE & | 1591 | DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); |
1706 | ~DP_PSR_MAIN_LINK_ACTIVE); | ||
1707 | else | 1592 | else |
1708 | intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, | 1593 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, |
1709 | DP_PSR_ENABLE | | 1594 | DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); |
1710 | DP_PSR_MAIN_LINK_ACTIVE); | ||
1711 | 1595 | ||
1712 | /* Setup AUX registers */ | 1596 | /* Setup AUX registers */ |
1713 | I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); | 1597 | I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); |
@@ -2018,26 +1902,25 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) | |||
2018 | /* | 1902 | /* |
2019 | * Native read with retry for link status and receiver capability reads for | 1903 | * Native read with retry for link status and receiver capability reads for |
2020 | * cases where the sink may still be asleep. | 1904 | * cases where the sink may still be asleep. |
1905 | * | ||
1906 | * Sinks are *supposed* to come up within 1ms from an off state, but we're also | ||
1907 | * supposed to retry 3 times per the spec. | ||
2021 | */ | 1908 | */ |
2022 | static bool | 1909 | static ssize_t |
2023 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, | 1910 | intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, |
2024 | uint8_t *recv, int recv_bytes) | 1911 | void *buffer, size_t size) |
2025 | { | 1912 | { |
2026 | int ret, i; | 1913 | ssize_t ret; |
1914 | int i; | ||
2027 | 1915 | ||
2028 | /* | ||
2029 | * Sinks are *supposed* to come up within 1ms from an off state, | ||
2030 | * but we're also supposed to retry 3 times per the spec. | ||
2031 | */ | ||
2032 | for (i = 0; i < 3; i++) { | 1916 | for (i = 0; i < 3; i++) { |
2033 | ret = intel_dp_aux_native_read(intel_dp, address, recv, | 1917 | ret = drm_dp_dpcd_read(aux, offset, buffer, size); |
2034 | recv_bytes); | 1918 | if (ret == size) |
2035 | if (ret == recv_bytes) | 1919 | return ret; |
2036 | return true; | ||
2037 | msleep(1); | 1920 | msleep(1); |
2038 | } | 1921 | } |
2039 | 1922 | ||
2040 | return false; | 1923 | return ret; |
2041 | } | 1924 | } |
2042 | 1925 | ||
2043 | /* | 1926 | /* |
@@ -2047,10 +1930,10 @@ intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, | |||
2047 | static bool | 1930 | static bool |
2048 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) | 1931 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
2049 | { | 1932 | { |
2050 | return intel_dp_aux_native_read_retry(intel_dp, | 1933 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
2051 | DP_LANE0_1_STATUS, | 1934 | DP_LANE0_1_STATUS, |
2052 | link_status, | 1935 | link_status, |
2053 | DP_LINK_STATUS_SIZE); | 1936 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; |
2054 | } | 1937 | } |
2055 | 1938 | ||
2056 | /* | 1939 | /* |
@@ -2564,8 +2447,8 @@ intel_dp_set_link_train(struct intel_dp *intel_dp, | |||
2564 | len = intel_dp->lane_count + 1; | 2447 | len = intel_dp->lane_count + 1; |
2565 | } | 2448 | } |
2566 | 2449 | ||
2567 | ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET, | 2450 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, |
2568 | buf, len); | 2451 | buf, len); |
2569 | 2452 | ||
2570 | return ret == len; | 2453 | return ret == len; |
2571 | } | 2454 | } |
@@ -2594,9 +2477,8 @@ intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, | |||
2594 | I915_WRITE(intel_dp->output_reg, *DP); | 2477 | I915_WRITE(intel_dp->output_reg, *DP); |
2595 | POSTING_READ(intel_dp->output_reg); | 2478 | POSTING_READ(intel_dp->output_reg); |
2596 | 2479 | ||
2597 | ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET, | 2480 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, |
2598 | intel_dp->train_set, | 2481 | intel_dp->train_set, intel_dp->lane_count); |
2599 | intel_dp->lane_count); | ||
2600 | 2482 | ||
2601 | return ret == intel_dp->lane_count; | 2483 | return ret == intel_dp->lane_count; |
2602 | } | 2484 | } |
@@ -2652,11 +2534,11 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) | |||
2652 | link_config[1] = intel_dp->lane_count; | 2534 | link_config[1] = intel_dp->lane_count; |
2653 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | 2535 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
2654 | link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; | 2536 | link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
2655 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2); | 2537 | drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); |
2656 | 2538 | ||
2657 | link_config[0] = 0; | 2539 | link_config[0] = 0; |
2658 | link_config[1] = DP_SET_ANSI_8B10B; | 2540 | link_config[1] = DP_SET_ANSI_8B10B; |
2659 | intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2); | 2541 | drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); |
2660 | 2542 | ||
2661 | DP |= DP_PORT_EN; | 2543 | DP |= DP_PORT_EN; |
2662 | 2544 | ||
@@ -2899,8 +2781,8 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) | |||
2899 | 2781 | ||
2900 | char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; | 2782 | char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; |
2901 | 2783 | ||
2902 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, | 2784 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, |
2903 | sizeof(intel_dp->dpcd)) == 0) | 2785 | sizeof(intel_dp->dpcd)) < 0) |
2904 | return false; /* aux transfer failed */ | 2786 | return false; /* aux transfer failed */ |
2905 | 2787 | ||
2906 | hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), | 2788 | hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), |
@@ -2913,9 +2795,9 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) | |||
2913 | /* Check if the panel supports PSR */ | 2795 | /* Check if the panel supports PSR */ |
2914 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); | 2796 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); |
2915 | if (is_edp(intel_dp)) { | 2797 | if (is_edp(intel_dp)) { |
2916 | intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT, | 2798 | intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, |
2917 | intel_dp->psr_dpcd, | 2799 | intel_dp->psr_dpcd, |
2918 | sizeof(intel_dp->psr_dpcd)); | 2800 | sizeof(intel_dp->psr_dpcd)); |
2919 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { | 2801 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
2920 | dev_priv->psr.sink_support = true; | 2802 | dev_priv->psr.sink_support = true; |
2921 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); | 2803 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
@@ -2937,9 +2819,9 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) | |||
2937 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) | 2819 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) |
2938 | return true; /* no per-port downstream info */ | 2820 | return true; /* no per-port downstream info */ |
2939 | 2821 | ||
2940 | if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0, | 2822 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
2941 | intel_dp->downstream_ports, | 2823 | intel_dp->downstream_ports, |
2942 | DP_MAX_DOWNSTREAM_PORTS) == 0) | 2824 | DP_MAX_DOWNSTREAM_PORTS) < 0) |
2943 | return false; /* downstream port status fetch failed */ | 2825 | return false; /* downstream port status fetch failed */ |
2944 | 2826 | ||
2945 | return true; | 2827 | return true; |
@@ -2955,11 +2837,11 @@ intel_dp_probe_oui(struct intel_dp *intel_dp) | |||
2955 | 2837 | ||
2956 | intel_edp_panel_vdd_on(intel_dp); | 2838 | intel_edp_panel_vdd_on(intel_dp); |
2957 | 2839 | ||
2958 | if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3)) | 2840 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
2959 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", | 2841 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
2960 | buf[0], buf[1], buf[2]); | 2842 | buf[0], buf[1], buf[2]); |
2961 | 2843 | ||
2962 | if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3)) | 2844 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
2963 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", | 2845 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
2964 | buf[0], buf[1], buf[2]); | 2846 | buf[0], buf[1], buf[2]); |
2965 | 2847 | ||
@@ -2974,46 +2856,40 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) | |||
2974 | to_intel_crtc(intel_dig_port->base.base.crtc); | 2856 | to_intel_crtc(intel_dig_port->base.base.crtc); |
2975 | u8 buf[1]; | 2857 | u8 buf[1]; |
2976 | 2858 | ||
2977 | if (!intel_dp_aux_native_read(intel_dp, DP_TEST_SINK_MISC, buf, 1)) | 2859 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0) |
2978 | return -EAGAIN; | 2860 | return -EAGAIN; |
2979 | 2861 | ||
2980 | if (!(buf[0] & DP_TEST_CRC_SUPPORTED)) | 2862 | if (!(buf[0] & DP_TEST_CRC_SUPPORTED)) |
2981 | return -ENOTTY; | 2863 | return -ENOTTY; |
2982 | 2864 | ||
2983 | if (!intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK, | 2865 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
2984 | DP_TEST_SINK_START)) | 2866 | DP_TEST_SINK_START) < 0) |
2985 | return -EAGAIN; | 2867 | return -EAGAIN; |
2986 | 2868 | ||
2987 | /* Wait 2 vblanks to be sure we will have the correct CRC value */ | 2869 | /* Wait 2 vblanks to be sure we will have the correct CRC value */ |
2988 | intel_wait_for_vblank(dev, intel_crtc->pipe); | 2870 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
2989 | intel_wait_for_vblank(dev, intel_crtc->pipe); | 2871 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
2990 | 2872 | ||
2991 | if (!intel_dp_aux_native_read(intel_dp, DP_TEST_CRC_R_CR, crc, 6)) | 2873 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) |
2992 | return -EAGAIN; | 2874 | return -EAGAIN; |
2993 | 2875 | ||
2994 | intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK, 0); | 2876 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0); |
2995 | return 0; | 2877 | return 0; |
2996 | } | 2878 | } |
2997 | 2879 | ||
2998 | static bool | 2880 | static bool |
2999 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | 2881 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
3000 | { | 2882 | { |
3001 | int ret; | 2883 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
3002 | 2884 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
3003 | ret = intel_dp_aux_native_read_retry(intel_dp, | 2885 | sink_irq_vector, 1) == 1; |
3004 | DP_DEVICE_SERVICE_IRQ_VECTOR, | ||
3005 | sink_irq_vector, 1); | ||
3006 | if (!ret) | ||
3007 | return false; | ||
3008 | |||
3009 | return true; | ||
3010 | } | 2886 | } |
3011 | 2887 | ||
3012 | static void | 2888 | static void |
3013 | intel_dp_handle_test_request(struct intel_dp *intel_dp) | 2889 | intel_dp_handle_test_request(struct intel_dp *intel_dp) |
3014 | { | 2890 | { |
3015 | /* NAK by default */ | 2891 | /* NAK by default */ |
3016 | intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK); | 2892 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK); |
3017 | } | 2893 | } |
3018 | 2894 | ||
3019 | /* | 2895 | /* |
@@ -3052,9 +2928,9 @@ intel_dp_check_link_status(struct intel_dp *intel_dp) | |||
3052 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | 2928 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
3053 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { | 2929 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
3054 | /* Clear interrupt source */ | 2930 | /* Clear interrupt source */ |
3055 | intel_dp_aux_native_write_1(intel_dp, | 2931 | drm_dp_dpcd_writeb(&intel_dp->aux, |
3056 | DP_DEVICE_SERVICE_IRQ_VECTOR, | 2932 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
3057 | sink_irq_vector); | 2933 | sink_irq_vector); |
3058 | 2934 | ||
3059 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | 2935 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
3060 | intel_dp_handle_test_request(intel_dp); | 2936 | intel_dp_handle_test_request(intel_dp); |
@@ -3089,15 +2965,17 @@ intel_dp_detect_dpcd(struct intel_dp *intel_dp) | |||
3089 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | 2965 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
3090 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { | 2966 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { |
3091 | uint8_t reg; | 2967 | uint8_t reg; |
3092 | if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT, | 2968 | |
3093 | ®, 1)) | 2969 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, |
2970 | ®, 1) < 0) | ||
3094 | return connector_status_unknown; | 2971 | return connector_status_unknown; |
2972 | |||
3095 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected | 2973 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
3096 | : connector_status_disconnected; | 2974 | : connector_status_disconnected; |
3097 | } | 2975 | } |
3098 | 2976 | ||
3099 | /* If no HPD, poke DDC gently */ | 2977 | /* If no HPD, poke DDC gently */ |
3100 | if (drm_probe_ddc(&intel_dp->adapter)) | 2978 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
3101 | return connector_status_connected; | 2979 | return connector_status_connected; |
3102 | 2980 | ||
3103 | /* Well we tried, say unknown for unreliable port types */ | 2981 | /* Well we tried, say unknown for unreliable port types */ |
@@ -3265,7 +3143,7 @@ intel_dp_detect(struct drm_connector *connector, bool force) | |||
3265 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { | 3143 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { |
3266 | intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); | 3144 | intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); |
3267 | } else { | 3145 | } else { |
3268 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); | 3146 | edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); |
3269 | if (edid) { | 3147 | if (edid) { |
3270 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | 3148 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
3271 | kfree(edid); | 3149 | kfree(edid); |
@@ -3301,7 +3179,7 @@ static int intel_dp_get_modes(struct drm_connector *connector) | |||
3301 | power_domain = intel_display_port_power_domain(intel_encoder); | 3179 | power_domain = intel_display_port_power_domain(intel_encoder); |
3302 | intel_display_power_get(dev_priv, power_domain); | 3180 | intel_display_power_get(dev_priv, power_domain); |
3303 | 3181 | ||
3304 | ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); | 3182 | ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc); |
3305 | intel_display_power_put(dev_priv, power_domain); | 3183 | intel_display_power_put(dev_priv, power_domain); |
3306 | if (ret) | 3184 | if (ret) |
3307 | return ret; | 3185 | return ret; |
@@ -3334,7 +3212,7 @@ intel_dp_detect_audio(struct drm_connector *connector) | |||
3334 | power_domain = intel_display_port_power_domain(intel_encoder); | 3212 | power_domain = intel_display_port_power_domain(intel_encoder); |
3335 | intel_display_power_get(dev_priv, power_domain); | 3213 | intel_display_power_get(dev_priv, power_domain); |
3336 | 3214 | ||
3337 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); | 3215 | edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); |
3338 | if (edid) { | 3216 | if (edid) { |
3339 | has_audio = drm_detect_monitor_audio(edid); | 3217 | has_audio = drm_detect_monitor_audio(edid); |
3340 | kfree(edid); | 3218 | kfree(edid); |
@@ -3456,7 +3334,7 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder) | |||
3456 | struct intel_dp *intel_dp = &intel_dig_port->dp; | 3334 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
3457 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | 3335 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3458 | 3336 | ||
3459 | i2c_del_adapter(&intel_dp->adapter); | 3337 | drm_dp_aux_unregister_i2c_bus(&intel_dp->aux); |
3460 | drm_encoder_cleanup(encoder); | 3338 | drm_encoder_cleanup(encoder); |
3461 | if (is_edp(intel_dp)) { | 3339 | if (is_edp(intel_dp)) { |
3462 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | 3340 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
@@ -3768,7 +3646,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, | |||
3768 | /* We now know it's not a ghost, init power sequence regs. */ | 3646 | /* We now know it's not a ghost, init power sequence regs. */ |
3769 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq); | 3647 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq); |
3770 | 3648 | ||
3771 | edid = drm_get_edid(connector, &intel_dp->adapter); | 3649 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
3772 | if (edid) { | 3650 | if (edid) { |
3773 | if (drm_add_edid_modes(connector, edid)) { | 3651 | if (drm_add_edid_modes(connector, edid)) { |
3774 | drm_mode_connector_update_edid_property(connector, | 3652 | drm_mode_connector_update_edid_property(connector, |
@@ -3816,8 +3694,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, | |||
3816 | struct drm_i915_private *dev_priv = dev->dev_private; | 3694 | struct drm_i915_private *dev_priv = dev->dev_private; |
3817 | enum port port = intel_dig_port->port; | 3695 | enum port port = intel_dig_port->port; |
3818 | struct edp_power_seq power_seq = { 0 }; | 3696 | struct edp_power_seq power_seq = { 0 }; |
3819 | const char *name = NULL; | 3697 | int type; |
3820 | int type, error; | ||
3821 | 3698 | ||
3822 | /* intel_dp vfuncs */ | 3699 | /* intel_dp vfuncs */ |
3823 | if (IS_VALLEYVIEW(dev)) | 3700 | if (IS_VALLEYVIEW(dev)) |
@@ -3870,43 +3747,19 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, | |||
3870 | intel_connector->get_hw_state = intel_connector_get_hw_state; | 3747 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
3871 | intel_connector->unregister = intel_dp_connector_unregister; | 3748 | intel_connector->unregister = intel_dp_connector_unregister; |
3872 | 3749 | ||
3873 | intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; | 3750 | /* Set up the hotplug pin. */ |
3874 | if (HAS_DDI(dev)) { | ||
3875 | switch (intel_dig_port->port) { | ||
3876 | case PORT_A: | ||
3877 | intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; | ||
3878 | break; | ||
3879 | case PORT_B: | ||
3880 | intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; | ||
3881 | break; | ||
3882 | case PORT_C: | ||
3883 | intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; | ||
3884 | break; | ||
3885 | case PORT_D: | ||
3886 | intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; | ||
3887 | break; | ||
3888 | default: | ||
3889 | BUG(); | ||
3890 | } | ||
3891 | } | ||
3892 | |||
3893 | /* Set up the DDC bus. */ | ||
3894 | switch (port) { | 3751 | switch (port) { |
3895 | case PORT_A: | 3752 | case PORT_A: |
3896 | intel_encoder->hpd_pin = HPD_PORT_A; | 3753 | intel_encoder->hpd_pin = HPD_PORT_A; |
3897 | name = "DPDDC-A"; | ||
3898 | break; | 3754 | break; |
3899 | case PORT_B: | 3755 | case PORT_B: |
3900 | intel_encoder->hpd_pin = HPD_PORT_B; | 3756 | intel_encoder->hpd_pin = HPD_PORT_B; |
3901 | name = "DPDDC-B"; | ||
3902 | break; | 3757 | break; |
3903 | case PORT_C: | 3758 | case PORT_C: |
3904 | intel_encoder->hpd_pin = HPD_PORT_C; | 3759 | intel_encoder->hpd_pin = HPD_PORT_C; |
3905 | name = "DPDDC-C"; | ||
3906 | break; | 3760 | break; |
3907 | case PORT_D: | 3761 | case PORT_D: |
3908 | intel_encoder->hpd_pin = HPD_PORT_D; | 3762 | intel_encoder->hpd_pin = HPD_PORT_D; |
3909 | name = "DPDDC-D"; | ||
3910 | break; | 3763 | break; |
3911 | default: | 3764 | default: |
3912 | BUG(); | 3765 | BUG(); |
@@ -3917,14 +3770,12 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, | |||
3917 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); | 3770 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
3918 | } | 3771 | } |
3919 | 3772 | ||
3920 | error = intel_dp_i2c_init(intel_dp, intel_connector, name); | 3773 | intel_dp_aux_init(intel_dp, intel_connector); |
3921 | WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n", | ||
3922 | error, port_name(port)); | ||
3923 | 3774 | ||
3924 | intel_dp->psr_setup_done = false; | 3775 | intel_dp->psr_setup_done = false; |
3925 | 3776 | ||
3926 | if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) { | 3777 | if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) { |
3927 | i2c_del_adapter(&intel_dp->adapter); | 3778 | drm_dp_aux_unregister_i2c_bus(&intel_dp->aux); |
3928 | if (is_edp(intel_dp)) { | 3779 | if (is_edp(intel_dp)) { |
3929 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | 3780 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
3930 | mutex_lock(&dev->mode_config.mutex); | 3781 | mutex_lock(&dev->mode_config.mutex); |