diff options
author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2012-10-23 16:30:01 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-10-26 04:24:48 -0400 |
commit | afe2fcf5e0ddca8aada0882fc5c54430101dfb0e (patch) | |
tree | 94cb15c7df5f834edb7a64025f437de3e9f4e3af /drivers/gpu/drm/i915/intel_dp.c | |
parent | c9809791ae0ae3e5792fc6ad3d4a5d9658aadc62 (diff) |
drm/i915: convert CPU M/N timings to transcoder
Same thing as the previous commits. Not renaming this one since it
exists since way before Haswell.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 01b67d911fa6..7e3c1deb80b1 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c | |||
@@ -777,6 +777,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |||
777 | int lane_count = 4; | 777 | int lane_count = 4; |
778 | struct intel_dp_m_n m_n; | 778 | struct intel_dp_m_n m_n; |
779 | int pipe = intel_crtc->pipe; | 779 | int pipe = intel_crtc->pipe; |
780 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; | ||
780 | 781 | ||
781 | /* | 782 | /* |
782 | * Find the lane count in the intel_encoder private | 783 | * Find the lane count in the intel_encoder private |
@@ -801,10 +802,11 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |||
801 | mode->clock, adjusted_mode->clock, &m_n); | 802 | mode->clock, adjusted_mode->clock, &m_n); |
802 | 803 | ||
803 | if (IS_HASWELL(dev)) { | 804 | if (IS_HASWELL(dev)) { |
804 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); | 805 | I915_WRITE(PIPE_DATA_M1(cpu_transcoder), |
805 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); | 806 | TU_SIZE(m_n.tu) | m_n.gmch_m); |
806 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); | 807 | I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n); |
807 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); | 808 | I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m); |
809 | I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n); | ||
808 | } else if (HAS_PCH_SPLIT(dev)) { | 810 | } else if (HAS_PCH_SPLIT(dev)) { |
809 | I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); | 811 | I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
810 | I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); | 812 | I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); |