drm/i915/chv: Don't use PCS group access reads

All PCS groups access reads return 0xffffffff, so we can't use group
access for RMW cycles. Instead target each spline separately.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
[danvet: Fight conflict with misplaced ; .... ARGH!]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 24 insertions, 8 deletions

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 37638f8e2265..d98de3c18621 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1882,13 +1882,21 @@ static void chv_post_disable_dp(struct intel_encoder *encoder)
         mutex_lock(&dev_priv->dpio_lock);
 
         /* Propagate soft reset to data lane reset */
-        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
         val |= CHV_PCS_REQ_SOFTRESET_EN;
-        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+        vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
 
-        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
+        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
+        val |= CHV_PCS_REQ_SOFTRESET_EN;
+        vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
+
+        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
+        val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+        vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
+
+        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
-        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
+        vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
 
         mutex_unlock(&dev_priv->dpio_lock);
 }
@@ -2027,13 +2035,21 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
         mutex_lock(&dev_priv->dpio_lock);
 
         /* Deassert soft data lane reset*/
-        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
+        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
         val |= CHV_PCS_REQ_SOFTRESET_EN;
-        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
+        vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
+
+        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
+        val |= CHV_PCS_REQ_SOFTRESET_EN;
+        vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
+
+        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
+        val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
+        vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
 
-        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
+        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
         val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
-        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
+        vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
 
         /* Program Tx lane latency optimal setting*/
         for (i = 0; i < 4; i++) {