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authorAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
committerAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
commitada47b5fe13d89735805b566185f4885f5a3f750 (patch)
tree644b88f8a71896307d71438e9b3af49126ffb22b /drivers/gpu/drm/i915/intel_dp.c
parent43e98717ad40a4ae64545b5ba047c7b86aa44f4f (diff)
parent3280f21d43ee541f97f8cda5792150d2dbec20d5 (diff)
Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c386
1 files changed, 231 insertions, 155 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d83447557f9b..77e40cfcf216 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -26,6 +26,7 @@
26 */ 26 */
27 27
28#include <linux/i2c.h> 28#include <linux/i2c.h>
29#include <linux/slab.h>
29#include "drmP.h" 30#include "drmP.h"
30#include "drm.h" 31#include "drm.h"
31#include "drm_crtc.h" 32#include "drm_crtc.h"
@@ -33,7 +34,8 @@
33#include "intel_drv.h" 34#include "intel_drv.h"
34#include "i915_drm.h" 35#include "i915_drm.h"
35#include "i915_drv.h" 36#include "i915_drv.h"
36#include "intel_dp.h" 37#include "drm_dp_helper.h"
38
37 39
38#define DP_LINK_STATUS_SIZE 6 40#define DP_LINK_STATUS_SIZE 6
39#define DP_LINK_CHECK_TIMEOUT (10 * 1000) 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
@@ -53,23 +55,23 @@ struct intel_dp_priv {
53 uint8_t link_bw; 55 uint8_t link_bw;
54 uint8_t lane_count; 56 uint8_t lane_count;
55 uint8_t dpcd[4]; 57 uint8_t dpcd[4];
56 struct intel_output *intel_output; 58 struct intel_encoder *intel_encoder;
57 struct i2c_adapter adapter; 59 struct i2c_adapter adapter;
58 struct i2c_algo_dp_aux_data algo; 60 struct i2c_algo_dp_aux_data algo;
59}; 61};
60 62
61static void 63static void
62intel_dp_link_train(struct intel_output *intel_output, uint32_t DP, 64intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
63 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]); 65 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
64 66
65static void 67static void
66intel_dp_link_down(struct intel_output *intel_output, uint32_t DP); 68intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP);
67 69
68void 70void
69intel_edp_link_config (struct intel_output *intel_output, 71intel_edp_link_config (struct intel_encoder *intel_encoder,
70 int *lane_num, int *link_bw) 72 int *lane_num, int *link_bw)
71{ 73{
72 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 74 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
73 75
74 *lane_num = dp_priv->lane_count; 76 *lane_num = dp_priv->lane_count;
75 if (dp_priv->link_bw == DP_LINK_BW_1_62) 77 if (dp_priv->link_bw == DP_LINK_BW_1_62)
@@ -79,9 +81,9 @@ intel_edp_link_config (struct intel_output *intel_output,
79} 81}
80 82
81static int 83static int
82intel_dp_max_lane_count(struct intel_output *intel_output) 84intel_dp_max_lane_count(struct intel_encoder *intel_encoder)
83{ 85{
84 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 86 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
85 int max_lane_count = 4; 87 int max_lane_count = 4;
86 88
87 if (dp_priv->dpcd[0] >= 0x11) { 89 if (dp_priv->dpcd[0] >= 0x11) {
@@ -97,9 +99,9 @@ intel_dp_max_lane_count(struct intel_output *intel_output)
97} 99}
98 100
99static int 101static int
100intel_dp_max_link_bw(struct intel_output *intel_output) 102intel_dp_max_link_bw(struct intel_encoder *intel_encoder)
101{ 103{
102 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 104 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
103 int max_link_bw = dp_priv->dpcd[1]; 105 int max_link_bw = dp_priv->dpcd[1];
104 106
105 switch (max_link_bw) { 107 switch (max_link_bw) {
@@ -124,20 +126,27 @@ intel_dp_link_clock(uint8_t link_bw)
124 126
125/* I think this is a fiction */ 127/* I think this is a fiction */
126static int 128static int
127intel_dp_link_required(int pixel_clock) 129intel_dp_link_required(struct drm_device *dev,
130 struct intel_encoder *intel_encoder, int pixel_clock)
128{ 131{
129 return pixel_clock * 3; 132 struct drm_i915_private *dev_priv = dev->dev_private;
133
134 if (IS_eDP(intel_encoder))
135 return (pixel_clock * dev_priv->edp_bpp) / 8;
136 else
137 return pixel_clock * 3;
130} 138}
131 139
132static int 140static int
133intel_dp_mode_valid(struct drm_connector *connector, 141intel_dp_mode_valid(struct drm_connector *connector,
134 struct drm_display_mode *mode) 142 struct drm_display_mode *mode)
135{ 143{
136 struct intel_output *intel_output = to_intel_output(connector); 144 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
137 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_output)); 145 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder));
138 int max_lanes = intel_dp_max_lane_count(intel_output); 146 int max_lanes = intel_dp_max_lane_count(intel_encoder);
139 147
140 if (intel_dp_link_required(mode->clock) > max_link_clock * max_lanes) 148 if (intel_dp_link_required(connector->dev, intel_encoder, mode->clock)
149 > max_link_clock * max_lanes)
141 return MODE_CLOCK_HIGH; 150 return MODE_CLOCK_HIGH;
142 151
143 if (mode->clock < 10000) 152 if (mode->clock < 10000)
@@ -200,13 +209,13 @@ intel_hrawclk(struct drm_device *dev)
200} 209}
201 210
202static int 211static int
203intel_dp_aux_ch(struct intel_output *intel_output, 212intel_dp_aux_ch(struct intel_encoder *intel_encoder,
204 uint8_t *send, int send_bytes, 213 uint8_t *send, int send_bytes,
205 uint8_t *recv, int recv_size) 214 uint8_t *recv, int recv_size)
206{ 215{
207 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 216 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
208 uint32_t output_reg = dp_priv->output_reg; 217 uint32_t output_reg = dp_priv->output_reg;
209 struct drm_device *dev = intel_output->base.dev; 218 struct drm_device *dev = intel_encoder->base.dev;
210 struct drm_i915_private *dev_priv = dev->dev_private; 219 struct drm_i915_private *dev_priv = dev->dev_private;
211 uint32_t ch_ctl = output_reg + 0x10; 220 uint32_t ch_ctl = output_reg + 0x10;
212 uint32_t ch_data = ch_ctl + 4; 221 uint32_t ch_data = ch_ctl + 4;
@@ -221,10 +230,10 @@ intel_dp_aux_ch(struct intel_output *intel_output,
221 * and would like to run at 2MHz. So, take the 230 * and would like to run at 2MHz. So, take the
222 * hrawclk value and divide by 2 and use that 231 * hrawclk value and divide by 2 and use that
223 */ 232 */
224 if (IS_eDP(intel_output)) 233 if (IS_eDP(intel_encoder))
225 aux_clock_divider = 225; /* eDP input clock at 450Mhz */ 234 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
226 else if (IS_IGDNG(dev)) 235 else if (HAS_PCH_SPLIT(dev))
227 aux_clock_divider = 62; /* IGDNG: input clock fixed at 125Mhz */ 236 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
228 else 237 else
229 aux_clock_divider = intel_hrawclk(dev) / 2; 238 aux_clock_divider = intel_hrawclk(dev) / 2;
230 239
@@ -282,7 +291,7 @@ intel_dp_aux_ch(struct intel_output *intel_output,
282 /* Timeouts occur when the device isn't connected, so they're 291 /* Timeouts occur when the device isn't connected, so they're
283 * "normal" -- don't fill the kernel log with these */ 292 * "normal" -- don't fill the kernel log with these */
284 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 293 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
285 DRM_DEBUG("dp_aux_ch timeout status 0x%08x\n", status); 294 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
286 return -ETIMEDOUT; 295 return -ETIMEDOUT;
287 } 296 }
288 297
@@ -304,7 +313,7 @@ intel_dp_aux_ch(struct intel_output *intel_output,
304 313
305/* Write data to the aux channel in native mode */ 314/* Write data to the aux channel in native mode */
306static int 315static int
307intel_dp_aux_native_write(struct intel_output *intel_output, 316intel_dp_aux_native_write(struct intel_encoder *intel_encoder,
308 uint16_t address, uint8_t *send, int send_bytes) 317 uint16_t address, uint8_t *send, int send_bytes)
309{ 318{
310 int ret; 319 int ret;
@@ -321,7 +330,7 @@ intel_dp_aux_native_write(struct intel_output *intel_output,
321 memcpy(&msg[4], send, send_bytes); 330 memcpy(&msg[4], send, send_bytes);
322 msg_bytes = send_bytes + 4; 331 msg_bytes = send_bytes + 4;
323 for (;;) { 332 for (;;) {
324 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes, &ack, 1); 333 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes, &ack, 1);
325 if (ret < 0) 334 if (ret < 0)
326 return ret; 335 return ret;
327 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 336 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
@@ -336,15 +345,15 @@ intel_dp_aux_native_write(struct intel_output *intel_output,
336 345
337/* Write a single byte to the aux channel in native mode */ 346/* Write a single byte to the aux channel in native mode */
338static int 347static int
339intel_dp_aux_native_write_1(struct intel_output *intel_output, 348intel_dp_aux_native_write_1(struct intel_encoder *intel_encoder,
340 uint16_t address, uint8_t byte) 349 uint16_t address, uint8_t byte)
341{ 350{
342 return intel_dp_aux_native_write(intel_output, address, &byte, 1); 351 return intel_dp_aux_native_write(intel_encoder, address, &byte, 1);
343} 352}
344 353
345/* read bytes from a native aux channel */ 354/* read bytes from a native aux channel */
346static int 355static int
347intel_dp_aux_native_read(struct intel_output *intel_output, 356intel_dp_aux_native_read(struct intel_encoder *intel_encoder,
348 uint16_t address, uint8_t *recv, int recv_bytes) 357 uint16_t address, uint8_t *recv, int recv_bytes)
349{ 358{
350 uint8_t msg[4]; 359 uint8_t msg[4];
@@ -363,7 +372,7 @@ intel_dp_aux_native_read(struct intel_output *intel_output,
363 reply_bytes = recv_bytes + 1; 372 reply_bytes = recv_bytes + 1;
364 373
365 for (;;) { 374 for (;;) {
366 ret = intel_dp_aux_ch(intel_output, msg, msg_bytes, 375 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes,
367 reply, reply_bytes); 376 reply, reply_bytes);
368 if (ret == 0) 377 if (ret == 0)
369 return -EPROTO; 378 return -EPROTO;
@@ -382,23 +391,83 @@ intel_dp_aux_native_read(struct intel_output *intel_output,
382} 391}
383 392
384static int 393static int
385intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, 394intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
386 uint8_t *send, int send_bytes, 395 uint8_t write_byte, uint8_t *read_byte)
387 uint8_t *recv, int recv_bytes)
388{ 396{
397 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
389 struct intel_dp_priv *dp_priv = container_of(adapter, 398 struct intel_dp_priv *dp_priv = container_of(adapter,
390 struct intel_dp_priv, 399 struct intel_dp_priv,
391 adapter); 400 adapter);
392 struct intel_output *intel_output = dp_priv->intel_output; 401 struct intel_encoder *intel_encoder = dp_priv->intel_encoder;
402 uint16_t address = algo_data->address;
403 uint8_t msg[5];
404 uint8_t reply[2];
405 int msg_bytes;
406 int reply_bytes;
407 int ret;
393 408
394 return intel_dp_aux_ch(intel_output, 409 /* Set up the command byte */
395 send, send_bytes, recv, recv_bytes); 410 if (mode & MODE_I2C_READ)
411 msg[0] = AUX_I2C_READ << 4;
412 else
413 msg[0] = AUX_I2C_WRITE << 4;
414
415 if (!(mode & MODE_I2C_STOP))
416 msg[0] |= AUX_I2C_MOT << 4;
417
418 msg[1] = address >> 8;
419 msg[2] = address;
420
421 switch (mode) {
422 case MODE_I2C_WRITE:
423 msg[3] = 0;
424 msg[4] = write_byte;
425 msg_bytes = 5;
426 reply_bytes = 1;
427 break;
428 case MODE_I2C_READ:
429 msg[3] = 0;
430 msg_bytes = 4;
431 reply_bytes = 2;
432 break;
433 default:
434 msg_bytes = 3;
435 reply_bytes = 1;
436 break;
437 }
438
439 for (;;) {
440 ret = intel_dp_aux_ch(intel_encoder,
441 msg, msg_bytes,
442 reply, reply_bytes);
443 if (ret < 0) {
444 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
445 return ret;
446 }
447 switch (reply[0] & AUX_I2C_REPLY_MASK) {
448 case AUX_I2C_REPLY_ACK:
449 if (mode == MODE_I2C_READ) {
450 *read_byte = reply[1];
451 }
452 return reply_bytes - 1;
453 case AUX_I2C_REPLY_NACK:
454 DRM_DEBUG_KMS("aux_ch nack\n");
455 return -EREMOTEIO;
456 case AUX_I2C_REPLY_DEFER:
457 DRM_DEBUG_KMS("aux_ch defer\n");
458 udelay(100);
459 break;
460 default:
461 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
462 return -EREMOTEIO;
463 }
464 }
396} 465}
397 466
398static int 467static int
399intel_dp_i2c_init(struct intel_output *intel_output, const char *name) 468intel_dp_i2c_init(struct intel_encoder *intel_encoder, const char *name)
400{ 469{
401 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 470 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
402 471
403 DRM_DEBUG_KMS("i2c_init %s\n", name); 472 DRM_DEBUG_KMS("i2c_init %s\n", name);
404 dp_priv->algo.running = false; 473 dp_priv->algo.running = false;
@@ -411,7 +480,7 @@ intel_dp_i2c_init(struct intel_output *intel_output, const char *name)
411 strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1); 480 strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1);
412 dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0'; 481 dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0';
413 dp_priv->adapter.algo_data = &dp_priv->algo; 482 dp_priv->adapter.algo_data = &dp_priv->algo;
414 dp_priv->adapter.dev.parent = &intel_output->base.kdev; 483 dp_priv->adapter.dev.parent = &intel_encoder->base.kdev;
415 484
416 return i2c_dp_aux_add_bus(&dp_priv->adapter); 485 return i2c_dp_aux_add_bus(&dp_priv->adapter);
417} 486}
@@ -420,22 +489,24 @@ static bool
420intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, 489intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
421 struct drm_display_mode *adjusted_mode) 490 struct drm_display_mode *adjusted_mode)
422{ 491{
423 struct intel_output *intel_output = enc_to_intel_output(encoder); 492 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
424 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 493 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
425 int lane_count, clock; 494 int lane_count, clock;
426 int max_lane_count = intel_dp_max_lane_count(intel_output); 495 int max_lane_count = intel_dp_max_lane_count(intel_encoder);
427 int max_clock = intel_dp_max_link_bw(intel_output) == DP_LINK_BW_2_7 ? 1 : 0; 496 int max_clock = intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0;
428 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 497 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
429 498
430 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 499 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
431 for (clock = 0; clock <= max_clock; clock++) { 500 for (clock = 0; clock <= max_clock; clock++) {
432 int link_avail = intel_dp_link_clock(bws[clock]) * lane_count; 501 int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
433 502
434 if (intel_dp_link_required(mode->clock) <= link_avail) { 503 if (intel_dp_link_required(encoder->dev, intel_encoder, mode->clock)
504 <= link_avail) {
435 dp_priv->link_bw = bws[clock]; 505 dp_priv->link_bw = bws[clock];
436 dp_priv->lane_count = lane_count; 506 dp_priv->lane_count = lane_count;
437 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw); 507 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
438 DRM_DEBUG("Display port link bw %02x lane count %d clock %d\n", 508 DRM_DEBUG_KMS("Display port link bw %02x lane "
509 "count %d clock %d\n",
439 dp_priv->link_bw, dp_priv->lane_count, 510 dp_priv->link_bw, dp_priv->lane_count,
440 adjusted_mode->clock); 511 adjusted_mode->clock);
441 return true; 512 return true;
@@ -491,16 +562,16 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
491 struct intel_dp_m_n m_n; 562 struct intel_dp_m_n m_n;
492 563
493 /* 564 /*
494 * Find the lane count in the intel_output private 565 * Find the lane count in the intel_encoder private
495 */ 566 */
496 list_for_each_entry(connector, &mode_config->connector_list, head) { 567 list_for_each_entry(connector, &mode_config->connector_list, head) {
497 struct intel_output *intel_output = to_intel_output(connector); 568 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
498 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 569 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
499 570
500 if (!connector->encoder || connector->encoder->crtc != crtc) 571 if (!connector->encoder || connector->encoder->crtc != crtc)
501 continue; 572 continue;
502 573
503 if (intel_output->type == INTEL_OUTPUT_DISPLAYPORT) { 574 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
504 lane_count = dp_priv->lane_count; 575 lane_count = dp_priv->lane_count;
505 break; 576 break;
506 } 577 }
@@ -514,7 +585,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
514 intel_dp_compute_m_n(3, lane_count, 585 intel_dp_compute_m_n(3, lane_count,
515 mode->clock, adjusted_mode->clock, &m_n); 586 mode->clock, adjusted_mode->clock, &m_n);
516 587
517 if (IS_IGDNG(dev)) { 588 if (HAS_PCH_SPLIT(dev)) {
518 if (intel_crtc->pipe == 0) { 589 if (intel_crtc->pipe == 0) {
519 I915_WRITE(TRANSA_DATA_M1, 590 I915_WRITE(TRANSA_DATA_M1,
520 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | 591 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
@@ -555,9 +626,9 @@ static void
555intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, 626intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
556 struct drm_display_mode *adjusted_mode) 627 struct drm_display_mode *adjusted_mode)
557{ 628{
558 struct intel_output *intel_output = enc_to_intel_output(encoder); 629 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
559 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 630 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
560 struct drm_crtc *crtc = intel_output->enc.crtc; 631 struct drm_crtc *crtc = intel_encoder->enc.crtc;
561 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 632 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
562 633
563 dp_priv->DP = (DP_LINK_TRAIN_OFF | 634 dp_priv->DP = (DP_LINK_TRAIN_OFF |
@@ -596,7 +667,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
596 if (intel_crtc->pipe == 1) 667 if (intel_crtc->pipe == 1)
597 dp_priv->DP |= DP_PIPEB_SELECT; 668 dp_priv->DP |= DP_PIPEB_SELECT;
598 669
599 if (IS_eDP(intel_output)) { 670 if (IS_eDP(intel_encoder)) {
600 /* don't miss out required setting for eDP */ 671 /* don't miss out required setting for eDP */
601 dp_priv->DP |= DP_PLL_ENABLE; 672 dp_priv->DP |= DP_PLL_ENABLE;
602 if (adjusted_mode->clock < 200000) 673 if (adjusted_mode->clock < 200000)
@@ -606,23 +677,23 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
606 } 677 }
607} 678}
608 679
609static void igdng_edp_backlight_on (struct drm_device *dev) 680static void ironlake_edp_backlight_on (struct drm_device *dev)
610{ 681{
611 struct drm_i915_private *dev_priv = dev->dev_private; 682 struct drm_i915_private *dev_priv = dev->dev_private;
612 u32 pp; 683 u32 pp;
613 684
614 DRM_DEBUG("\n"); 685 DRM_DEBUG_KMS("\n");
615 pp = I915_READ(PCH_PP_CONTROL); 686 pp = I915_READ(PCH_PP_CONTROL);
616 pp |= EDP_BLC_ENABLE; 687 pp |= EDP_BLC_ENABLE;
617 I915_WRITE(PCH_PP_CONTROL, pp); 688 I915_WRITE(PCH_PP_CONTROL, pp);
618} 689}
619 690
620static void igdng_edp_backlight_off (struct drm_device *dev) 691static void ironlake_edp_backlight_off (struct drm_device *dev)
621{ 692{
622 struct drm_i915_private *dev_priv = dev->dev_private; 693 struct drm_i915_private *dev_priv = dev->dev_private;
623 u32 pp; 694 u32 pp;
624 695
625 DRM_DEBUG("\n"); 696 DRM_DEBUG_KMS("\n");
626 pp = I915_READ(PCH_PP_CONTROL); 697 pp = I915_READ(PCH_PP_CONTROL);
627 pp &= ~EDP_BLC_ENABLE; 698 pp &= ~EDP_BLC_ENABLE;
628 I915_WRITE(PCH_PP_CONTROL, pp); 699 I915_WRITE(PCH_PP_CONTROL, pp);
@@ -631,23 +702,23 @@ static void igdng_edp_backlight_off (struct drm_device *dev)
631static void 702static void
632intel_dp_dpms(struct drm_encoder *encoder, int mode) 703intel_dp_dpms(struct drm_encoder *encoder, int mode)
633{ 704{
634 struct intel_output *intel_output = enc_to_intel_output(encoder); 705 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
635 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 706 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
636 struct drm_device *dev = intel_output->base.dev; 707 struct drm_device *dev = intel_encoder->base.dev;
637 struct drm_i915_private *dev_priv = dev->dev_private; 708 struct drm_i915_private *dev_priv = dev->dev_private;
638 uint32_t dp_reg = I915_READ(dp_priv->output_reg); 709 uint32_t dp_reg = I915_READ(dp_priv->output_reg);
639 710
640 if (mode != DRM_MODE_DPMS_ON) { 711 if (mode != DRM_MODE_DPMS_ON) {
641 if (dp_reg & DP_PORT_EN) { 712 if (dp_reg & DP_PORT_EN) {
642 intel_dp_link_down(intel_output, dp_priv->DP); 713 intel_dp_link_down(intel_encoder, dp_priv->DP);
643 if (IS_eDP(intel_output)) 714 if (IS_eDP(intel_encoder))
644 igdng_edp_backlight_off(dev); 715 ironlake_edp_backlight_off(dev);
645 } 716 }
646 } else { 717 } else {
647 if (!(dp_reg & DP_PORT_EN)) { 718 if (!(dp_reg & DP_PORT_EN)) {
648 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration); 719 intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
649 if (IS_eDP(intel_output)) 720 if (IS_eDP(intel_encoder))
650 igdng_edp_backlight_on(dev); 721 ironlake_edp_backlight_on(dev);
651 } 722 }
652 } 723 }
653 dp_priv->dpms_mode = mode; 724 dp_priv->dpms_mode = mode;
@@ -658,12 +729,12 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
658 * link status information 729 * link status information
659 */ 730 */
660static bool 731static bool
661intel_dp_get_link_status(struct intel_output *intel_output, 732intel_dp_get_link_status(struct intel_encoder *intel_encoder,
662 uint8_t link_status[DP_LINK_STATUS_SIZE]) 733 uint8_t link_status[DP_LINK_STATUS_SIZE])
663{ 734{
664 int ret; 735 int ret;
665 736
666 ret = intel_dp_aux_native_read(intel_output, 737 ret = intel_dp_aux_native_read(intel_encoder,
667 DP_LANE0_1_STATUS, 738 DP_LANE0_1_STATUS,
668 link_status, DP_LINK_STATUS_SIZE); 739 link_status, DP_LINK_STATUS_SIZE);
669 if (ret != DP_LINK_STATUS_SIZE) 740 if (ret != DP_LINK_STATUS_SIZE)
@@ -681,13 +752,13 @@ intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
681static void 752static void
682intel_dp_save(struct drm_connector *connector) 753intel_dp_save(struct drm_connector *connector)
683{ 754{
684 struct intel_output *intel_output = to_intel_output(connector); 755 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
685 struct drm_device *dev = intel_output->base.dev; 756 struct drm_device *dev = intel_encoder->base.dev;
686 struct drm_i915_private *dev_priv = dev->dev_private; 757 struct drm_i915_private *dev_priv = dev->dev_private;
687 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 758 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
688 759
689 dp_priv->save_DP = I915_READ(dp_priv->output_reg); 760 dp_priv->save_DP = I915_READ(dp_priv->output_reg);
690 intel_dp_aux_native_read(intel_output, DP_LINK_BW_SET, 761 intel_dp_aux_native_read(intel_encoder, DP_LINK_BW_SET,
691 dp_priv->save_link_configuration, 762 dp_priv->save_link_configuration,
692 sizeof (dp_priv->save_link_configuration)); 763 sizeof (dp_priv->save_link_configuration));
693} 764}
@@ -754,7 +825,7 @@ intel_dp_pre_emphasis_max(uint8_t voltage_swing)
754} 825}
755 826
756static void 827static void
757intel_get_adjust_train(struct intel_output *intel_output, 828intel_get_adjust_train(struct intel_encoder *intel_encoder,
758 uint8_t link_status[DP_LINK_STATUS_SIZE], 829 uint8_t link_status[DP_LINK_STATUS_SIZE],
759 int lane_count, 830 int lane_count,
760 uint8_t train_set[4]) 831 uint8_t train_set[4])
@@ -871,15 +942,15 @@ intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
871} 942}
872 943
873static bool 944static bool
874intel_dp_set_link_train(struct intel_output *intel_output, 945intel_dp_set_link_train(struct intel_encoder *intel_encoder,
875 uint32_t dp_reg_value, 946 uint32_t dp_reg_value,
876 uint8_t dp_train_pat, 947 uint8_t dp_train_pat,
877 uint8_t train_set[4], 948 uint8_t train_set[4],
878 bool first) 949 bool first)
879{ 950{
880 struct drm_device *dev = intel_output->base.dev; 951 struct drm_device *dev = intel_encoder->base.dev;
881 struct drm_i915_private *dev_priv = dev->dev_private; 952 struct drm_i915_private *dev_priv = dev->dev_private;
882 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 953 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
883 int ret; 954 int ret;
884 955
885 I915_WRITE(dp_priv->output_reg, dp_reg_value); 956 I915_WRITE(dp_priv->output_reg, dp_reg_value);
@@ -887,11 +958,11 @@ intel_dp_set_link_train(struct intel_output *intel_output,
887 if (first) 958 if (first)
888 intel_wait_for_vblank(dev); 959 intel_wait_for_vblank(dev);
889 960
890 intel_dp_aux_native_write_1(intel_output, 961 intel_dp_aux_native_write_1(intel_encoder,
891 DP_TRAINING_PATTERN_SET, 962 DP_TRAINING_PATTERN_SET,
892 dp_train_pat); 963 dp_train_pat);
893 964
894 ret = intel_dp_aux_native_write(intel_output, 965 ret = intel_dp_aux_native_write(intel_encoder,
895 DP_TRAINING_LANE0_SET, train_set, 4); 966 DP_TRAINING_LANE0_SET, train_set, 4);
896 if (ret != 4) 967 if (ret != 4)
897 return false; 968 return false;
@@ -900,12 +971,12 @@ intel_dp_set_link_train(struct intel_output *intel_output,
900} 971}
901 972
902static void 973static void
903intel_dp_link_train(struct intel_output *intel_output, uint32_t DP, 974intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
904 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]) 975 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
905{ 976{
906 struct drm_device *dev = intel_output->base.dev; 977 struct drm_device *dev = intel_encoder->base.dev;
907 struct drm_i915_private *dev_priv = dev->dev_private; 978 struct drm_i915_private *dev_priv = dev->dev_private;
908 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 979 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
909 uint8_t train_set[4]; 980 uint8_t train_set[4];
910 uint8_t link_status[DP_LINK_STATUS_SIZE]; 981 uint8_t link_status[DP_LINK_STATUS_SIZE];
911 int i; 982 int i;
@@ -916,7 +987,7 @@ intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
916 int tries; 987 int tries;
917 988
918 /* Write the link configuration data */ 989 /* Write the link configuration data */
919 intel_dp_aux_native_write(intel_output, 0x100, 990 intel_dp_aux_native_write(intel_encoder, 0x100,
920 link_configuration, DP_LINK_CONFIGURATION_SIZE); 991 link_configuration, DP_LINK_CONFIGURATION_SIZE);
921 992
922 DP |= DP_PORT_EN; 993 DP |= DP_PORT_EN;
@@ -930,14 +1001,14 @@ intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
930 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count); 1001 uint32_t signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
931 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1002 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
932 1003
933 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_1, 1004 if (!intel_dp_set_link_train(intel_encoder, DP | DP_LINK_TRAIN_PAT_1,
934 DP_TRAINING_PATTERN_1, train_set, first)) 1005 DP_TRAINING_PATTERN_1, train_set, first))
935 break; 1006 break;
936 first = false; 1007 first = false;
937 /* Set training pattern 1 */ 1008 /* Set training pattern 1 */
938 1009
939 udelay(100); 1010 udelay(100);
940 if (!intel_dp_get_link_status(intel_output, link_status)) 1011 if (!intel_dp_get_link_status(intel_encoder, link_status))
941 break; 1012 break;
942 1013
943 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) { 1014 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
@@ -962,7 +1033,7 @@ intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
962 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 1033 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
963 1034
964 /* Compute new train_set as requested by target */ 1035 /* Compute new train_set as requested by target */
965 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set); 1036 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
966 } 1037 }
967 1038
968 /* channel equalization */ 1039 /* channel equalization */
@@ -974,13 +1045,13 @@ intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
974 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1045 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
975 1046
976 /* channel eq pattern */ 1047 /* channel eq pattern */
977 if (!intel_dp_set_link_train(intel_output, DP | DP_LINK_TRAIN_PAT_2, 1048 if (!intel_dp_set_link_train(intel_encoder, DP | DP_LINK_TRAIN_PAT_2,
978 DP_TRAINING_PATTERN_2, train_set, 1049 DP_TRAINING_PATTERN_2, train_set,
979 false)) 1050 false))
980 break; 1051 break;
981 1052
982 udelay(400); 1053 udelay(400);
983 if (!intel_dp_get_link_status(intel_output, link_status)) 1054 if (!intel_dp_get_link_status(intel_encoder, link_status))
984 break; 1055 break;
985 1056
986 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) { 1057 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
@@ -993,26 +1064,26 @@ intel_dp_link_train(struct intel_output *intel_output, uint32_t DP,
993 break; 1064 break;
994 1065
995 /* Compute new train_set as requested by target */ 1066 /* Compute new train_set as requested by target */
996 intel_get_adjust_train(intel_output, link_status, dp_priv->lane_count, train_set); 1067 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
997 ++tries; 1068 ++tries;
998 } 1069 }
999 1070
1000 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_OFF); 1071 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_OFF);
1001 POSTING_READ(dp_priv->output_reg); 1072 POSTING_READ(dp_priv->output_reg);
1002 intel_dp_aux_native_write_1(intel_output, 1073 intel_dp_aux_native_write_1(intel_encoder,
1003 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); 1074 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1004} 1075}
1005 1076
1006static void 1077static void
1007intel_dp_link_down(struct intel_output *intel_output, uint32_t DP) 1078intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP)
1008{ 1079{
1009 struct drm_device *dev = intel_output->base.dev; 1080 struct drm_device *dev = intel_encoder->base.dev;
1010 struct drm_i915_private *dev_priv = dev->dev_private; 1081 struct drm_i915_private *dev_priv = dev->dev_private;
1011 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 1082 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1012 1083
1013 DRM_DEBUG("\n"); 1084 DRM_DEBUG_KMS("\n");
1014 1085
1015 if (IS_eDP(intel_output)) { 1086 if (IS_eDP(intel_encoder)) {
1016 DP &= ~DP_PLL_ENABLE; 1087 DP &= ~DP_PLL_ENABLE;
1017 I915_WRITE(dp_priv->output_reg, DP); 1088 I915_WRITE(dp_priv->output_reg, DP);
1018 POSTING_READ(dp_priv->output_reg); 1089 POSTING_READ(dp_priv->output_reg);
@@ -1025,7 +1096,7 @@ intel_dp_link_down(struct intel_output *intel_output, uint32_t DP)
1025 1096
1026 udelay(17000); 1097 udelay(17000);
1027 1098
1028 if (IS_eDP(intel_output)) 1099 if (IS_eDP(intel_encoder))
1029 DP |= DP_LINK_TRAIN_OFF; 1100 DP |= DP_LINK_TRAIN_OFF;
1030 I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN); 1101 I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
1031 POSTING_READ(dp_priv->output_reg); 1102 POSTING_READ(dp_priv->output_reg);
@@ -1034,13 +1105,13 @@ intel_dp_link_down(struct intel_output *intel_output, uint32_t DP)
1034static void 1105static void
1035intel_dp_restore(struct drm_connector *connector) 1106intel_dp_restore(struct drm_connector *connector)
1036{ 1107{
1037 struct intel_output *intel_output = to_intel_output(connector); 1108 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1038 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 1109 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1039 1110
1040 if (dp_priv->save_DP & DP_PORT_EN) 1111 if (dp_priv->save_DP & DP_PORT_EN)
1041 intel_dp_link_train(intel_output, dp_priv->save_DP, dp_priv->save_link_configuration); 1112 intel_dp_link_train(intel_encoder, dp_priv->save_DP, dp_priv->save_link_configuration);
1042 else 1113 else
1043 intel_dp_link_down(intel_output, dp_priv->save_DP); 1114 intel_dp_link_down(intel_encoder, dp_priv->save_DP);
1044} 1115}
1045 1116
1046/* 1117/*
@@ -1053,32 +1124,32 @@ intel_dp_restore(struct drm_connector *connector)
1053 */ 1124 */
1054 1125
1055static void 1126static void
1056intel_dp_check_link_status(struct intel_output *intel_output) 1127intel_dp_check_link_status(struct intel_encoder *intel_encoder)
1057{ 1128{
1058 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 1129 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1059 uint8_t link_status[DP_LINK_STATUS_SIZE]; 1130 uint8_t link_status[DP_LINK_STATUS_SIZE];
1060 1131
1061 if (!intel_output->enc.crtc) 1132 if (!intel_encoder->enc.crtc)
1062 return; 1133 return;
1063 1134
1064 if (!intel_dp_get_link_status(intel_output, link_status)) { 1135 if (!intel_dp_get_link_status(intel_encoder, link_status)) {
1065 intel_dp_link_down(intel_output, dp_priv->DP); 1136 intel_dp_link_down(intel_encoder, dp_priv->DP);
1066 return; 1137 return;
1067 } 1138 }
1068 1139
1069 if (!intel_channel_eq_ok(link_status, dp_priv->lane_count)) 1140 if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
1070 intel_dp_link_train(intel_output, dp_priv->DP, dp_priv->link_configuration); 1141 intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
1071} 1142}
1072 1143
1073static enum drm_connector_status 1144static enum drm_connector_status
1074igdng_dp_detect(struct drm_connector *connector) 1145ironlake_dp_detect(struct drm_connector *connector)
1075{ 1146{
1076 struct intel_output *intel_output = to_intel_output(connector); 1147 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1077 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 1148 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1078 enum drm_connector_status status; 1149 enum drm_connector_status status;
1079 1150
1080 status = connector_status_disconnected; 1151 status = connector_status_disconnected;
1081 if (intel_dp_aux_native_read(intel_output, 1152 if (intel_dp_aux_native_read(intel_encoder,
1082 0x000, dp_priv->dpcd, 1153 0x000, dp_priv->dpcd,
1083 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd)) 1154 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1084 { 1155 {
@@ -1097,17 +1168,17 @@ igdng_dp_detect(struct drm_connector *connector)
1097static enum drm_connector_status 1168static enum drm_connector_status
1098intel_dp_detect(struct drm_connector *connector) 1169intel_dp_detect(struct drm_connector *connector)
1099{ 1170{
1100 struct intel_output *intel_output = to_intel_output(connector); 1171 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1101 struct drm_device *dev = intel_output->base.dev; 1172 struct drm_device *dev = intel_encoder->base.dev;
1102 struct drm_i915_private *dev_priv = dev->dev_private; 1173 struct drm_i915_private *dev_priv = dev->dev_private;
1103 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 1174 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1104 uint32_t temp, bit; 1175 uint32_t temp, bit;
1105 enum drm_connector_status status; 1176 enum drm_connector_status status;
1106 1177
1107 dp_priv->has_audio = false; 1178 dp_priv->has_audio = false;
1108 1179
1109 if (IS_IGDNG(dev)) 1180 if (HAS_PCH_SPLIT(dev))
1110 return igdng_dp_detect(connector); 1181 return ironlake_dp_detect(connector);
1111 1182
1112 temp = I915_READ(PORT_HOTPLUG_EN); 1183 temp = I915_READ(PORT_HOTPLUG_EN);
1113 1184
@@ -1139,7 +1210,7 @@ intel_dp_detect(struct drm_connector *connector)
1139 return connector_status_disconnected; 1210 return connector_status_disconnected;
1140 1211
1141 status = connector_status_disconnected; 1212 status = connector_status_disconnected;
1142 if (intel_dp_aux_native_read(intel_output, 1213 if (intel_dp_aux_native_read(intel_encoder,
1143 0x000, dp_priv->dpcd, 1214 0x000, dp_priv->dpcd,
1144 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd)) 1215 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1145 { 1216 {
@@ -1151,20 +1222,20 @@ intel_dp_detect(struct drm_connector *connector)
1151 1222
1152static int intel_dp_get_modes(struct drm_connector *connector) 1223static int intel_dp_get_modes(struct drm_connector *connector)
1153{ 1224{
1154 struct intel_output *intel_output = to_intel_output(connector); 1225 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1155 struct drm_device *dev = intel_output->base.dev; 1226 struct drm_device *dev = intel_encoder->base.dev;
1156 struct drm_i915_private *dev_priv = dev->dev_private; 1227 struct drm_i915_private *dev_priv = dev->dev_private;
1157 int ret; 1228 int ret;
1158 1229
1159 /* We should parse the EDID data and find out if it has an audio sink 1230 /* We should parse the EDID data and find out if it has an audio sink
1160 */ 1231 */
1161 1232
1162 ret = intel_ddc_get_modes(intel_output); 1233 ret = intel_ddc_get_modes(intel_encoder);
1163 if (ret) 1234 if (ret)
1164 return ret; 1235 return ret;
1165 1236
1166 /* if eDP has no EDID, try to use fixed panel mode from VBT */ 1237 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1167 if (IS_eDP(intel_output)) { 1238 if (IS_eDP(intel_encoder)) {
1168 if (dev_priv->panel_fixed_mode != NULL) { 1239 if (dev_priv->panel_fixed_mode != NULL) {
1169 struct drm_display_mode *mode; 1240 struct drm_display_mode *mode;
1170 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); 1241 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
@@ -1178,13 +1249,13 @@ static int intel_dp_get_modes(struct drm_connector *connector)
1178static void 1249static void
1179intel_dp_destroy (struct drm_connector *connector) 1250intel_dp_destroy (struct drm_connector *connector)
1180{ 1251{
1181 struct intel_output *intel_output = to_intel_output(connector); 1252 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1182 1253
1183 if (intel_output->i2c_bus) 1254 if (intel_encoder->i2c_bus)
1184 intel_i2c_destroy(intel_output->i2c_bus); 1255 intel_i2c_destroy(intel_encoder->i2c_bus);
1185 drm_sysfs_connector_remove(connector); 1256 drm_sysfs_connector_remove(connector);
1186 drm_connector_cleanup(connector); 1257 drm_connector_cleanup(connector);
1187 kfree(intel_output); 1258 kfree(intel_encoder);
1188} 1259}
1189 1260
1190static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { 1261static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
@@ -1220,12 +1291,12 @@ static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1220}; 1291};
1221 1292
1222void 1293void
1223intel_dp_hot_plug(struct intel_output *intel_output) 1294intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1224{ 1295{
1225 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 1296 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1226 1297
1227 if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON) 1298 if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
1228 intel_dp_check_link_status(intel_output); 1299 intel_dp_check_link_status(intel_encoder);
1229} 1300}
1230 1301
1231void 1302void
@@ -1233,54 +1304,53 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1233{ 1304{
1234 struct drm_i915_private *dev_priv = dev->dev_private; 1305 struct drm_i915_private *dev_priv = dev->dev_private;
1235 struct drm_connector *connector; 1306 struct drm_connector *connector;
1236 struct intel_output *intel_output; 1307 struct intel_encoder *intel_encoder;
1237 struct intel_dp_priv *dp_priv; 1308 struct intel_dp_priv *dp_priv;
1238 const char *name = NULL; 1309 const char *name = NULL;
1239 1310
1240 intel_output = kcalloc(sizeof(struct intel_output) + 1311 intel_encoder = kcalloc(sizeof(struct intel_encoder) +
1241 sizeof(struct intel_dp_priv), 1, GFP_KERNEL); 1312 sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
1242 if (!intel_output) 1313 if (!intel_encoder)
1243 return; 1314 return;
1244 1315
1245 dp_priv = (struct intel_dp_priv *)(intel_output + 1); 1316 dp_priv = (struct intel_dp_priv *)(intel_encoder + 1);
1246 1317
1247 connector = &intel_output->base; 1318 connector = &intel_encoder->base;
1248 drm_connector_init(dev, connector, &intel_dp_connector_funcs, 1319 drm_connector_init(dev, connector, &intel_dp_connector_funcs,
1249 DRM_MODE_CONNECTOR_DisplayPort); 1320 DRM_MODE_CONNECTOR_DisplayPort);
1250 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 1321 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1251 1322
1252 if (output_reg == DP_A) 1323 if (output_reg == DP_A)
1253 intel_output->type = INTEL_OUTPUT_EDP; 1324 intel_encoder->type = INTEL_OUTPUT_EDP;
1254 else 1325 else
1255 intel_output->type = INTEL_OUTPUT_DISPLAYPORT; 1326 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1256 1327
1257 if (output_reg == DP_B) 1328 if (output_reg == DP_B || output_reg == PCH_DP_B)
1258 intel_output->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); 1329 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1259 else if (output_reg == DP_C) 1330 else if (output_reg == DP_C || output_reg == PCH_DP_C)
1260 intel_output->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); 1331 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1261 else if (output_reg == DP_D) 1332 else if (output_reg == DP_D || output_reg == PCH_DP_D)
1262 intel_output->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); 1333 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1263 1334
1264 if (IS_eDP(intel_output)) { 1335 if (IS_eDP(intel_encoder))
1265 intel_output->crtc_mask = (1 << 1); 1336 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1266 intel_output->clone_mask = (1 << INTEL_EDP_CLONE_BIT); 1337
1267 } else 1338 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1268 intel_output->crtc_mask = (1 << 0) | (1 << 1);
1269 connector->interlace_allowed = true; 1339 connector->interlace_allowed = true;
1270 connector->doublescan_allowed = 0; 1340 connector->doublescan_allowed = 0;
1271 1341
1272 dp_priv->intel_output = intel_output; 1342 dp_priv->intel_encoder = intel_encoder;
1273 dp_priv->output_reg = output_reg; 1343 dp_priv->output_reg = output_reg;
1274 dp_priv->has_audio = false; 1344 dp_priv->has_audio = false;
1275 dp_priv->dpms_mode = DRM_MODE_DPMS_ON; 1345 dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
1276 intel_output->dev_priv = dp_priv; 1346 intel_encoder->dev_priv = dp_priv;
1277 1347
1278 drm_encoder_init(dev, &intel_output->enc, &intel_dp_enc_funcs, 1348 drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs,
1279 DRM_MODE_ENCODER_TMDS); 1349 DRM_MODE_ENCODER_TMDS);
1280 drm_encoder_helper_add(&intel_output->enc, &intel_dp_helper_funcs); 1350 drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs);
1281 1351
1282 drm_mode_connector_attach_encoder(&intel_output->base, 1352 drm_mode_connector_attach_encoder(&intel_encoder->base,
1283 &intel_output->enc); 1353 &intel_encoder->enc);
1284 drm_sysfs_connector_add(connector); 1354 drm_sysfs_connector_add(connector);
1285 1355
1286 /* Set up the DDC bus. */ 1356 /* Set up the DDC bus. */
@@ -1290,22 +1360,28 @@ intel_dp_init(struct drm_device *dev, int output_reg)
1290 break; 1360 break;
1291 case DP_B: 1361 case DP_B:
1292 case PCH_DP_B: 1362 case PCH_DP_B:
1363 dev_priv->hotplug_supported_mask |=
1364 HDMIB_HOTPLUG_INT_STATUS;
1293 name = "DPDDC-B"; 1365 name = "DPDDC-B";
1294 break; 1366 break;
1295 case DP_C: 1367 case DP_C:
1296 case PCH_DP_C: 1368 case PCH_DP_C:
1369 dev_priv->hotplug_supported_mask |=
1370 HDMIC_HOTPLUG_INT_STATUS;
1297 name = "DPDDC-C"; 1371 name = "DPDDC-C";
1298 break; 1372 break;
1299 case DP_D: 1373 case DP_D:
1300 case PCH_DP_D: 1374 case PCH_DP_D:
1375 dev_priv->hotplug_supported_mask |=
1376 HDMID_HOTPLUG_INT_STATUS;
1301 name = "DPDDC-D"; 1377 name = "DPDDC-D";
1302 break; 1378 break;
1303 } 1379 }
1304 1380
1305 intel_dp_i2c_init(intel_output, name); 1381 intel_dp_i2c_init(intel_encoder, name);
1306 1382
1307 intel_output->ddc_bus = &dp_priv->adapter; 1383 intel_encoder->ddc_bus = &dp_priv->adapter;
1308 intel_output->hot_plug = intel_dp_hot_plug; 1384 intel_encoder->hot_plug = intel_dp_hot_plug;
1309 1385
1310 if (output_reg == DP_A) { 1386 if (output_reg == DP_A) {
1311 /* initialize panel mode from VBT if available for eDP */ 1387 /* initialize panel mode from VBT if available for eDP */