diff options
author | Chris Wilson <chris@chris-wilson.co.uk> | 2011-01-08 04:02:21 -0500 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2011-01-11 15:44:54 -0500 |
commit | db66e37d239b45f36a3f6495cf4ec49391b2c089 (patch) | |
tree | d16899c361fb77e7732eb603835cb95c3af49421 /drivers/gpu/drm/i915/intel_display.c | |
parent | 882417851a0f2e09e110038a13e88e9b5a100800 (diff) |
drm/i915: Include TLB miss overhead for computing WM
The docs recommend that if 8 display lines fit inside the FIFO buffer,
then the number of watermark entries should be increased to hide the
latency of filling the rest of the FIFO buffer.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 1190efa390bd..25d96889d7d2 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -3425,8 +3425,9 @@ static bool ironlake_compute_wm0(struct drm_device *dev, | |||
3425 | int *cursor_wm) | 3425 | int *cursor_wm) |
3426 | { | 3426 | { |
3427 | struct drm_crtc *crtc; | 3427 | struct drm_crtc *crtc; |
3428 | int htotal, hdisplay, clock, pixel_size = 0; | 3428 | int htotal, hdisplay, clock, pixel_size; |
3429 | int line_time_us, line_count, entries; | 3429 | int line_time_us, line_count; |
3430 | int entries, tlb_miss; | ||
3430 | 3431 | ||
3431 | crtc = intel_get_crtc_for_pipe(dev, pipe); | 3432 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
3432 | if (crtc->fb == NULL || !crtc->enabled) | 3433 | if (crtc->fb == NULL || !crtc->enabled) |
@@ -3439,6 +3440,9 @@ static bool ironlake_compute_wm0(struct drm_device *dev, | |||
3439 | 3440 | ||
3440 | /* Use the small buffer method to calculate plane watermark */ | 3441 | /* Use the small buffer method to calculate plane watermark */ |
3441 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | 3442 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
3443 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; | ||
3444 | if (tlb_miss > 0) | ||
3445 | entries += tlb_miss; | ||
3442 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | 3446 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
3443 | *plane_wm = entries + display->guard_size; | 3447 | *plane_wm = entries + display->guard_size; |
3444 | if (*plane_wm > (int)display->max_wm) | 3448 | if (*plane_wm > (int)display->max_wm) |
@@ -3448,6 +3452,9 @@ static bool ironlake_compute_wm0(struct drm_device *dev, | |||
3448 | line_time_us = ((htotal * 1000) / clock); | 3452 | line_time_us = ((htotal * 1000) / clock); |
3449 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; | 3453 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
3450 | entries = line_count * 64 * pixel_size; | 3454 | entries = line_count * 64 * pixel_size; |
3455 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; | ||
3456 | if (tlb_miss > 0) | ||
3457 | entries += tlb_miss; | ||
3451 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | 3458 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
3452 | *cursor_wm = entries + cursor->guard_size; | 3459 | *cursor_wm = entries + cursor->guard_size; |
3453 | if (*cursor_wm > (int)cursor->max_wm) | 3460 | if (*cursor_wm > (int)cursor->max_wm) |