drm/i915: Make i9xx_crtc_clock_get() work for PCH DPLLs

Add the 120MHz refernce clock case for PCH DPLLs.

Also determine the reference clock frequency more accurately by
checking for the PLLB_REF_INPUT_SPREADSPECTRUMIN refclk input
mode. The gen2 code already checked it, but it stil assumed a
fixed 66MHz refclk. Instead we need to consult the VBT for the
real value.

v2: Fix refclk for SSC panel case

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 21 insertions, 11 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 38f2b306a109..e1c6a5547f68 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7341,6 +7341,22 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
         mutex_unlock(&crtc->mutex);
 }
 
+static int i9xx_pll_refclk(struct drm_device *dev,
+                           const struct intel_crtc_config *pipe_config)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 dpll = pipe_config->dpll_hw_state.dpll;
+
+        if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
+                return dev_priv->vbt.lvds_ssc_freq * 1000;
+        else if (HAS_PCH_SPLIT(dev))
+                return 120000;
+        else if (!IS_GEN2(dev))
+                return 96000;
+        else
+                return 48000;
+}
+
 /* Returns the clock of the currently programmed mode of the given pipe. */
 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
                                 struct intel_crtc_config *pipe_config)
@@ -7351,6 +7367,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
         u32 dpll = pipe_config->dpll_hw_state.dpll;
         u32 fp;
         intel_clock_t clock;
+        int refclk = i9xx_pll_refclk(dev, pipe_config);
 
         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
                 fp = pipe_config->dpll_hw_state.fp0;
@@ -7390,9 +7407,9 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
                 }
 
                 if (IS_PINEVIEW(dev))
-                        pineview_clock(96000, &clock);
+                        pineview_clock(refclk, &clock);
                 else
-                        i9xx_clock(96000, &clock);
+                        i9xx_clock(refclk, &clock);
         } else {
                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
 
@@ -7400,13 +7417,6 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
                         clock.p2 = 14;
-
-                        if ((dpll & PLL_REF_INPUT_MASK) ==
-                            PLLB_REF_INPUT_SPREADSPECTRUMIN) {
-                                /* XXX: might not be 66MHz */
-                                i9xx_clock(66000, &clock);
-                        } else
-                                i9xx_clock(48000, &clock);
                 } else {
                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
                                 clock.p1 = 2;
@@ -7418,9 +7428,9 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
                                 clock.p2 = 4;
                         else
                                 clock.p2 = 2;
-
-                        i9xx_clock(48000, &clock);
                 }
+
+                i9xx_clock(refclk, &clock);
         }
 
         pipe_config->adjusted_mode.clock = clock.dot;