Merge tag 'drm-intel-next-2014-07-25-merged' of git://anongit.freedesktop.org/drm-intel into drm-next

Final feature pull for 3.17.

drm-intel-next-2014-07-25:
- Ditch UMS support (well just the config option for now)
- Prep work for future platforms (Sonika Jindal, Damien)
- runtime pm/soix fixes (Paulo, Jesse)
- psr tracking improvements, locking fixes, now enabled by default!
- rps fixes for chv (Deepak, Ville)
- drm core patches for rotation support (Ville, Sagar Kamble) - the i915 parts
  unfortunately didn't make it yet
- userptr fixes (Chris)
- minimum backlight brightness (Jani), acked long ago by Matthew Garret on irc -
  I've forgotten about this patch :(

QA is a bit unhappy about the DP MST stuff since it broke hpd testing a
bit, but otherwise looks sane. I've backmerged drm-next to resolve
conflicts with the mst stuff, which means the new tag itself doesn't
contain the overview as usual.

* tag 'drm-intel-next-2014-07-25-merged' of git://anongit.freedesktop.org/drm-intel: (75 commits)
  drm/i915/userptr: Keep spin_lock/unlock in the same block
  drm/i915: Allow overlapping userptr objects
  drm/i915: Ditch UMS config option
  drm/i915: respect the VBT minimum backlight brightness
  drm/i915: extract backlight minimum brightness from VBT
  drm/i915: Replace HAS_PCH_SPLIT which incorrectly lets some platforms in
  drm/i915: Returning from increase/decrease of pllclock when invalid
  drm/i915: Setting legacy palette correctly for different platforms
  drm/i915: Avoid incorrect returning for some platforms
  drm/i915: Writing proper check for reading of pipe status reg
  drm/i915: Returning the right VGA control reg for platforms
  drm/i915: Allowing changing of wm latencies for valid platforms
  drm/i915: Adding HAS_GMCH_DISPLAY macro
  drm/i915: Fix possible overflow when recording semaphore states.
  drm/i915: Do not unmap object unless no other VMAs reference it
  drm/i915: remove plane/cursor/pipe assertions from intel_crtc_disable
  drm/i915: Reorder ctx unref on ppgtt cleanup
  drm/i915/error: Check the potential ctx obj's vm
  drm/i915: Fix printing proper min/min/rpe values in debugfs
  drm/i915: BDW can also detect unclaimed registers
  ...

1 files changed, 39 insertions, 39 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7b542b477a4e..0f861301a94e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3855,7 +3855,7 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
         }
 
         /* use legacy palette for Ironlake */
-        if (HAS_PCH_SPLIT(dev))
+        if (!HAS_GMCH_DISPLAY(dev))
                 palreg = LGC_PALETTE(pipe);
 
         /* Workaround : Do not read or write the pipe palette/gamma data while
@@ -4894,35 +4894,21 @@ static void intel_crtc_update_sarea(struct drm_crtc *crtc,
         }
 }
 
-/**
- * Sets the power management mode of the pipe and plane.
- */
-void intel_crtc_update_dpms(struct drm_crtc *crtc)
+/* Master function to enable/disable CRTC and corresponding power wells */
+void intel_crtc_control(struct drm_crtc *crtc, bool enable)
 {
         struct drm_device *dev = crtc->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-        struct intel_encoder *intel_encoder;
         enum intel_display_power_domain domain;
         unsigned long domains;
-        bool enable = false;
-
-        for_each_encoder_on_crtc(dev, crtc, intel_encoder)
-                enable |= intel_encoder->connectors_active;
 
         if (enable) {
                 if (!intel_crtc->active) {
-                        /*
-                         * FIXME: DDI plls and relevant code isn't converted
-                         * yet, so do runtime PM for DPMS only for all other
-                         * platforms for now.
-                         */
-                        if (!HAS_DDI(dev)) {
-                                domains = get_crtc_power_domains(crtc);
-                                for_each_power_domain(domain, domains)
-                                        intel_display_power_get(dev_priv, domain);
-                                intel_crtc->enabled_power_domains = domains;
-                        }
+                        domains = get_crtc_power_domains(crtc);
+                        for_each_power_domain(domain, domains)
+                                intel_display_power_get(dev_priv, domain);
+                        intel_crtc->enabled_power_domains = domains;
 
                         dev_priv->display.crtc_enable(crtc);
                 }
@@ -4930,14 +4916,27 @@ void intel_crtc_update_dpms(struct drm_crtc *crtc)
                 if (intel_crtc->active) {
                         dev_priv->display.crtc_disable(crtc);
 
-                        if (!HAS_DDI(dev)) {
-                                domains = intel_crtc->enabled_power_domains;
-                                for_each_power_domain(domain, domains)
-                                        intel_display_power_put(dev_priv, domain);
-                                intel_crtc->enabled_power_domains = 0;
-                        }
+                        domains = intel_crtc->enabled_power_domains;
+                        for_each_power_domain(domain, domains)
+                                intel_display_power_put(dev_priv, domain);
+                        intel_crtc->enabled_power_domains = 0;
                 }
         }
+}
+
+/**
+ * Sets the power management mode of the pipe and plane.
+ */
+void intel_crtc_update_dpms(struct drm_crtc *crtc)
+{
+        struct drm_device *dev = crtc->dev;
+        struct intel_encoder *intel_encoder;
+        bool enable = false;
+
+        for_each_encoder_on_crtc(dev, crtc, intel_encoder)
+                enable |= intel_encoder->connectors_active;
+
+        intel_crtc_control(crtc, enable);
 
         intel_crtc_update_sarea(crtc, enable);
 }
@@ -4957,10 +4956,6 @@ static void intel_crtc_disable(struct drm_crtc *crtc)
         intel_crtc_update_sarea(crtc, false);
         dev_priv->display.off(crtc);
 
-        assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
-        assert_cursor_disabled(dev_priv, pipe);
-        assert_pipe_disabled(dev->dev_private, pipe);
-
         if (crtc->primary->fb) {
                 mutex_lock(&dev->struct_mutex);
                 intel_unpin_fb_obj(old_obj);
@@ -7360,8 +7355,9 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
              "CPU PWM1 enabled\n");
-        WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
-             "CPU PWM2 enabled\n");
+        if (IS_HASWELL(dev))
+                WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
+                     "CPU PWM2 enabled\n");
         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
              "PCH PWM1 enabled\n");
         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
@@ -7374,7 +7370,7 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
          * gen-specific and since we only disable LCPLL after we fully disable
          * the interrupts, the check below should be enough.
          */
-        WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
+        WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
 }
 
 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
@@ -8817,7 +8813,7 @@ static void intel_increase_pllclock(struct drm_device *dev,
         int dpll_reg = DPLL(pipe);
         int dpll;
 
-        if (HAS_PCH_SPLIT(dev))
+        if (!HAS_GMCH_DISPLAY(dev))
                 return;
 
         if (!dev_priv->lvds_downclock_avail)
@@ -8845,7 +8841,7 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 
-        if (HAS_PCH_SPLIT(dev))
+        if (!HAS_GMCH_DISPLAY(dev))
                 return;
 
         if (!dev_priv->lvds_downclock_avail)
@@ -8976,7 +8972,7 @@ void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
 
         intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
 
-        intel_edp_psr_exit(dev);
+        intel_edp_psr_invalidate(dev, obj->frontbuffer_bits);
 }
 
 /**
@@ -9002,7 +8998,7 @@ void intel_frontbuffer_flush(struct drm_device *dev,
 
         intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
 
-        intel_edp_psr_exit(dev);
+        intel_edp_psr_flush(dev, frontbuffer_bits);
 }
 
 /**
@@ -12825,6 +12821,8 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
                                       encoder->base.base.id,
                                       encoder->base.name);
                         encoder->disable(encoder);
+                        if (encoder->post_disable)
+                                encoder->post_disable(encoder);
                 }
                 encoder->base.crtc = NULL;
                 encoder->connectors_active = false;
@@ -13093,6 +13091,8 @@ void intel_modeset_cleanup(struct drm_device *dev)
          */
         drm_irq_uninstall(dev);
         cancel_work_sync(&dev_priv->hotplug_work);
+        dev_priv->pm._irqs_disabled = true;
+
         /*
          * Due to the hpd irq storm handling the hotplug work can re-arm the
          * poll handlers. Hence disable polling after hpd handling is shut down.
@@ -13270,7 +13270,7 @@ intel_display_capture_error_state(struct drm_device *dev)
 
                 error->pipe[i].source = I915_READ(PIPESRC(i));
 
-                if (!HAS_PCH_SPLIT(dev))
+                if (HAS_GMCH_DISPLAY(dev))
                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
         }