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authorDaniel Vetter <daniel.vetter@ffwll.ch>2014-06-25 15:01:57 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-07-10 16:11:46 -0400
commit9cd86933fe250fd3e698b62505dfe2d43326baaa (patch)
tree491b416afede1bc47045dca70a554093a8a25bd7 /drivers/gpu/drm/i915/intel_display.c
parent0e50338cf0f0009a5c9bc847a4c86a1d4438af66 (diff)
drm/i915: Basic shared dpll support for WRPLLs
Just filing in names and ids, but not yet officially registering them so that the hw state cross checker doesn't completely freak out about them. Still since we do already read out and cross check config->shared_dpll the basics are now there to flesh out the wrpll shared dpll implementation. The idea is now to roll out all the callbacks step-by-step and then at the end switch to the shared dpll framework. This way hw and sw changes are clearly separated. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> [imre: added const to hsw_ddi_pll_names (Damien)] Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c21
1 files changed, 13 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e26df6783406..0874f3589722 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7583,6 +7583,16 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7583 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; 7583 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7584 7584
7585 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); 7585 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7586
7587 switch (pipe_config->ddi_pll_sel) {
7588 case PORT_CLK_SEL_WRPLL1:
7589 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7590 break;
7591 case PORT_CLK_SEL_WRPLL2:
7592 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7593 break;
7594 }
7595
7586 /* 7596 /*
7587 * Haswell has only FDI/PCH transcoder A. It is which is connected to 7597 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7588 * DDI E. So just check whether this pipe is wired to DDI E and whether 7598 * DDI E. So just check whether this pipe is wired to DDI E and whether
@@ -11286,12 +11296,6 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
11286 .page_flip = intel_crtc_page_flip, 11296 .page_flip = intel_crtc_page_flip,
11287}; 11297};
11288 11298
11289static void intel_cpu_pll_init(struct drm_device *dev)
11290{
11291 if (HAS_DDI(dev))
11292 intel_ddi_pll_init(dev);
11293}
11294
11295static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, 11299static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11296 struct intel_shared_dpll *pll, 11300 struct intel_shared_dpll *pll,
11297 struct intel_dpll_hw_state *hw_state) 11301 struct intel_dpll_hw_state *hw_state)
@@ -11379,7 +11383,9 @@ static void intel_shared_dpll_init(struct drm_device *dev)
11379{ 11383{
11380 struct drm_i915_private *dev_priv = dev->dev_private; 11384 struct drm_i915_private *dev_priv = dev->dev_private;
11381 11385
11382 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) 11386 if (HAS_DDI(dev))
11387 intel_ddi_pll_init(dev);
11388 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11383 ibx_pch_dpll_init(dev); 11389 ibx_pch_dpll_init(dev);
11384 else 11390 else
11385 dev_priv->num_shared_dpll = 0; 11391 dev_priv->num_shared_dpll = 0;
@@ -12536,7 +12542,6 @@ void intel_modeset_init(struct drm_device *dev)
12536 intel_init_dpio(dev); 12542 intel_init_dpio(dev);
12537 intel_reset_dpio(dev); 12543 intel_reset_dpio(dev);
12538 12544
12539 intel_cpu_pll_init(dev);
12540 intel_shared_dpll_init(dev); 12545 intel_shared_dpll_init(dev);
12541 12546
12542 /* Just disable it once at startup */ 12547 /* Just disable it once at startup */