diff options
author | Damien Lespiau <damien.lespiau@intel.com> | 2014-07-29 13:06:18 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-08-08 11:43:35 -0400 |
commit | 7d2c81751c858442387fa5158d4cd80c2190d739 (patch) | |
tree | e889ea350891b27552ca2ee248c21e2780a0f28b /drivers/gpu/drm/i915/intel_display.c | |
parent | 74dd69280bc3f3e84d46b2a0f78901a0d9b4562c (diff) |
drm/i915: Extract the HSW DDI selection code into its own function
Future platform will slightly change that.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 27 |
1 files changed, 17 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 0b8769b9422f..c3bb5f7fd21b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -7607,6 +7607,22 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc, | |||
7607 | return 0; | 7607 | return 0; |
7608 | } | 7608 | } |
7609 | 7609 | ||
7610 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, | ||
7611 | enum port port, | ||
7612 | struct intel_crtc_config *pipe_config) | ||
7613 | { | ||
7614 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | ||
7615 | |||
7616 | switch (pipe_config->ddi_pll_sel) { | ||
7617 | case PORT_CLK_SEL_WRPLL1: | ||
7618 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | ||
7619 | break; | ||
7620 | case PORT_CLK_SEL_WRPLL2: | ||
7621 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | ||
7622 | break; | ||
7623 | } | ||
7624 | } | ||
7625 | |||
7610 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, | 7626 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
7611 | struct intel_crtc_config *pipe_config) | 7627 | struct intel_crtc_config *pipe_config) |
7612 | { | 7628 | { |
@@ -7620,16 +7636,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, | |||
7620 | 7636 | ||
7621 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | 7637 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; |
7622 | 7638 | ||
7623 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | 7639 | haswell_get_ddi_pll(dev_priv, port, pipe_config); |
7624 | |||
7625 | switch (pipe_config->ddi_pll_sel) { | ||
7626 | case PORT_CLK_SEL_WRPLL1: | ||
7627 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | ||
7628 | break; | ||
7629 | case PORT_CLK_SEL_WRPLL2: | ||
7630 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | ||
7631 | break; | ||
7632 | } | ||
7633 | 7640 | ||
7634 | if (pipe_config->shared_dpll >= 0) { | 7641 | if (pipe_config->shared_dpll >= 0) { |
7635 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | 7642 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; |