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author | Paul Mundt <lethal@linux-sh.org> | 2011-01-26 04:23:27 -0500 |
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committer | Paul Mundt <lethal@linux-sh.org> | 2011-01-26 04:23:27 -0500 |
commit | 6b620478e58677bb3f4ec884abb29ef9d68c7821 (patch) | |
tree | 7a438fc5412587f9bd9b907d4d423ea52a498006 /drivers/gpu/drm/i915/intel_display.c | |
parent | 906b17dc089f7fa87e37a9cfe6ee185efc90e0da (diff) | |
parent | 6fb1b304255efc5c4c93874ac8c066272e257e28 (diff) |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6 into common/serial-rework
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 25 |
1 files changed, 24 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 98967f3b7724..d7f237deaaf0 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -1213,6 +1213,26 @@ static bool g4x_fbc_enabled(struct drm_device *dev) | |||
1213 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; | 1213 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
1214 | } | 1214 | } |
1215 | 1215 | ||
1216 | static void sandybridge_blit_fbc_update(struct drm_device *dev) | ||
1217 | { | ||
1218 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
1219 | u32 blt_ecoskpd; | ||
1220 | |||
1221 | /* Make sure blitter notifies FBC of writes */ | ||
1222 | __gen6_force_wake_get(dev_priv); | ||
1223 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); | ||
1224 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << | ||
1225 | GEN6_BLITTER_LOCK_SHIFT; | ||
1226 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | ||
1227 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; | ||
1228 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | ||
1229 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << | ||
1230 | GEN6_BLITTER_LOCK_SHIFT); | ||
1231 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | ||
1232 | POSTING_READ(GEN6_BLITTER_ECOSKPD); | ||
1233 | __gen6_force_wake_put(dev_priv); | ||
1234 | } | ||
1235 | |||
1216 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | 1236 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1217 | { | 1237 | { |
1218 | struct drm_device *dev = crtc->dev; | 1238 | struct drm_device *dev = crtc->dev; |
@@ -1266,6 +1286,7 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | |||
1266 | I915_WRITE(SNB_DPFC_CTL_SA, | 1286 | I915_WRITE(SNB_DPFC_CTL_SA, |
1267 | SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence); | 1287 | SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence); |
1268 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); | 1288 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); |
1289 | sandybridge_blit_fbc_update(dev); | ||
1269 | } | 1290 | } |
1270 | 1291 | ||
1271 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); | 1292 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
@@ -6286,7 +6307,9 @@ void intel_enable_clock_gating(struct drm_device *dev) | |||
6286 | 6307 | ||
6287 | if (IS_GEN5(dev)) { | 6308 | if (IS_GEN5(dev)) { |
6288 | /* Required for FBC */ | 6309 | /* Required for FBC */ |
6289 | dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE; | 6310 | dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE | |
6311 | DPFCRUNIT_CLOCK_GATE_DISABLE | | ||
6312 | DPFDUNIT_CLOCK_GATE_DISABLE; | ||
6290 | /* Required for CxSR */ | 6313 | /* Required for CxSR */ |
6291 | dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; | 6314 | dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; |
6292 | 6315 | ||