drm/i915/chv: Reset data lanes in encoder .post_disable() hook

Seems like we shouldn't leave the data lane resert deasserted when
the port if disabled. So propagate the reset the data lanes in
the encoder .post_disable() hook.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 1 insertions, 6 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 21103a547aa7..bcb0c2eafde0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5515,7 +5515,7 @@ static void chv_update_pll(struct intel_crtc *crtc)
         int pipe = crtc->pipe;
         int dpll_reg = DPLL(crtc->pipe);
         enum dpio_channel port = vlv_pipe_to_channel(pipe);
-        u32 val, loopfilter, intcoeff;
+        u32 loopfilter, intcoeff;
         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
         int refclk;
 
@@ -5543,11 +5543,6 @@ static void chv_update_pll(struct intel_crtc *crtc)
 
         mutex_lock(&dev_priv->dpio_lock);
 
-        /* Propagate soft reset to data lane reset */
-        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(port));
-        val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
-        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), val);
-
         /* p1 and p2 divider */
         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
                         5 << DPIO_CHV_S1_DIV_SHIFT |