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authorVille Syrjälä <ville.syrjala@linux.intel.com>2013-10-09 10:24:58 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-10-10 06:47:14 -0400
commit4c445e0ebc648ee42c0d21713b8f76597854d47a (patch)
treed18626390d5324a79a05113f578c1bf8dc20f26c /drivers/gpu/drm/i915/intel_display.c
parente5b611fd4493d09eb5164f5244ac0a5325346895 (diff)
drm/i915: Rename primary_disabled to primary_enabled
Let's try to avoid these confusing negated booleans. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b54a4cf899f9..ebe5d0840a86 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1840,9 +1840,9 @@ static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1840 /* If the pipe isn't enabled, we can't pump pixels and may hang */ 1840 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1841 assert_pipe_enabled(dev_priv, pipe); 1841 assert_pipe_enabled(dev_priv, pipe);
1842 1842
1843 WARN(!intel_crtc->primary_disabled, "Primary plane already enabled\n"); 1843 WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1844 1844
1845 intel_crtc->primary_disabled = false; 1845 intel_crtc->primary_enabled = true;
1846 1846
1847 reg = DSPCNTR(plane); 1847 reg = DSPCNTR(plane);
1848 val = I915_READ(reg); 1848 val = I915_READ(reg);
@@ -1870,9 +1870,9 @@ static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1870 int reg; 1870 int reg;
1871 u32 val; 1871 u32 val;
1872 1872
1873 WARN(intel_crtc->primary_disabled, "Primary plane already disabled\n"); 1873 WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1874 1874
1875 intel_crtc->primary_disabled = true; 1875 intel_crtc->primary_enabled = false;
1876 1876
1877 reg = DSPCNTR(plane); 1877 reg = DSPCNTR(plane);
1878 val = I915_READ(reg); 1878 val = I915_READ(reg);
@@ -10706,7 +10706,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
10706 &crtc->config); 10706 &crtc->config);
10707 10707
10708 crtc->base.enabled = crtc->active; 10708 crtc->base.enabled = crtc->active;
10709 crtc->primary_disabled = !crtc->active; 10709 crtc->primary_enabled = crtc->active;
10710 10710
10711 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", 10711 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10712 crtc->base.base.id, 10712 crtc->base.base.id,