Merge remote branch 'anholt/drm-intel-next' into drm-next

* anholt/drm-intel-next: (515 commits)
  drm/i915: Fix out of tree builds
  drm/i915: move fence lru to struct drm_i915_fence_reg
  drm/i915: don't allow tiling changes on pinned buffers v2
  drm/i915: Be extra careful about A/D matching for multifunction SDVO
  drm/i915: Fix DDC bus selection for multifunction SDVO
  drm/i915: cleanup mode setting before unmapping registers
  drm/i915: Make fbc control wrapper functions
  drm/i915: Wait for the GPU whilst shrinking, if truly desperate.
  drm/i915: Use spatio-temporal dithering on PCH
  [MTD] Remove zero-length files mtdbdi.c and internal.ho
  pata_pcmcia / ide-cs: Fix bad hashes for Transcend and kingston IDs
  libata: Fix several inaccuracies in developer's guide
  slub: Fix bad boundary check in init_kmem_cache_nodes()
  raid6: fix recovery performance regression
  KEYS: call_sbin_request_key() must write lock keyrings before modifying them
  KEYS: Use RCU dereference wrappers in keyring key type code
  KEYS: find_keyring_by_name() can gain access to a freed keyring
  ALSA: hda: Fix 0 dB for Packard Bell models using Conexant CX20549 (Venice)
  ALSA: hda - Add quirk for Dell Inspiron 19T using a Conexant CX20582
  ALSA: take tu->qlock with irqs disabled
  ...

1 files changed, 56 insertions, 31 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4d739a1b13ca..8c668e3122a5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1048,9 +1048,8 @@ void i8xx_disable_fbc(struct drm_device *dev)
         DRM_DEBUG_KMS("disabled FBC\n");
 }
 
-static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
+static bool i8xx_fbc_enabled(struct drm_device *dev)
 {
-        struct drm_device *dev = crtc->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
 
         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
@@ -1107,14 +1106,43 @@ void g4x_disable_fbc(struct drm_device *dev)
         DRM_DEBUG_KMS("disabled FBC\n");
 }
 
-static bool g4x_fbc_enabled(struct drm_crtc *crtc)
+static bool g4x_fbc_enabled(struct drm_device *dev)
 {
-        struct drm_device *dev = crtc->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
 
         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 }
 
+bool intel_fbc_enabled(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        if (!dev_priv->display.fbc_enabled)
+                return false;
+
+        return dev_priv->display.fbc_enabled(dev);
+}
+
+void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
+{
+        struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+
+        if (!dev_priv->display.enable_fbc)
+                return;
+
+        dev_priv->display.enable_fbc(crtc, interval);
+}
+
+void intel_disable_fbc(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        if (!dev_priv->display.disable_fbc)
+                return;
+
+        dev_priv->display.disable_fbc(dev);
+}
+
 /**
  * intel_update_fbc - enable/disable FBC as needed
  * @crtc: CRTC to point the compressor at
@@ -1149,9 +1177,7 @@ static void intel_update_fbc(struct drm_crtc *crtc,
         if (!i915_powersave)
                 return;
 
-        if (!dev_priv->display.fbc_enabled ||
-            !dev_priv->display.enable_fbc ||
-            !dev_priv->display.disable_fbc)
+        if (!I915_HAS_FBC(dev))
                 return;
 
         if (!crtc->fb)
@@ -1198,28 +1224,25 @@ static void intel_update_fbc(struct drm_crtc *crtc,
                 goto out_disable;
         }
 
-        if (dev_priv->display.fbc_enabled(crtc)) {
+        if (intel_fbc_enabled(dev)) {
                 /* We can re-enable it in this case, but need to update pitch */
-                if (fb->pitch > dev_priv->cfb_pitch)
-                        dev_priv->display.disable_fbc(dev);
-                if (obj_priv->fence_reg != dev_priv->cfb_fence)
-                        dev_priv->display.disable_fbc(dev);
-                if (plane != dev_priv->cfb_plane)
-                        dev_priv->display.disable_fbc(dev);
+                if ((fb->pitch > dev_priv->cfb_pitch) ||
+                    (obj_priv->fence_reg != dev_priv->cfb_fence) ||
+                    (plane != dev_priv->cfb_plane))
+                        intel_disable_fbc(dev);
         }
 
-        if (!dev_priv->display.fbc_enabled(crtc)) {
-                /* Now try to turn it back on if possible */
-                dev_priv->display.enable_fbc(crtc, 500);
-        }
+        /* Now try to turn it back on if possible */
+        if (!intel_fbc_enabled(dev))
+                intel_enable_fbc(crtc, 500);
 
         return;
 
 out_disable:
         DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
         /* Multiple disables should be harmless */
-        if (dev_priv->display.fbc_enabled(crtc))
-                dev_priv->display.disable_fbc(dev);
+        if (intel_fbc_enabled(dev))
+                intel_disable_fbc(dev);
 }
 
 static int
@@ -3677,14 +3700,16 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                 /* set the dithering flag */
                 if (IS_I965G(dev)) {
                         if (dev_priv->lvds_dither) {
-                                if (HAS_PCH_SPLIT(dev))
+                                if (HAS_PCH_SPLIT(dev)) {
                                         pipeconf |= PIPE_ENABLE_DITHER;
-                                else
+                                        pipeconf |= PIPE_DITHER_TYPE_ST01;
+                                } else
                                         lvds |= LVDS_ENABLE_DITHER;
                         } else {
-                                if (HAS_PCH_SPLIT(dev))
+                                if (HAS_PCH_SPLIT(dev)) {
                                         pipeconf &= ~PIPE_ENABLE_DITHER;
-                                else
+                                        pipeconf &= ~PIPE_DITHER_TYPE_MASK;
+                                } else
                                         lvds &= ~LVDS_ENABLE_DITHER;
                         }
                 }
@@ -5202,8 +5227,7 @@ static void intel_init_display(struct drm_device *dev)
         else
                 dev_priv->display.dpms = i9xx_crtc_dpms;
 
-        /* Only mobile has FBC, leave pointers NULL for other chips */
-        if (IS_MOBILE(dev)) {
+        if (I915_HAS_FBC(dev)) {
                 if (IS_GM45(dev)) {
                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
                         dev_priv->display.enable_fbc = g4x_enable_fbc;
@@ -5268,17 +5292,18 @@ static void intel_init_display(struct drm_device *dev)
                 dev_priv->display.update_wm = g4x_update_wm;
         else if (IS_I965G(dev))
                 dev_priv->display.update_wm = i965_update_wm;
-        else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
+        else if (IS_I9XX(dev)) {
                 dev_priv->display.update_wm = i9xx_update_wm;
                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
+        } else if (IS_I85X(dev)) {
+                dev_priv->display.update_wm = i9xx_update_wm;
+                dev_priv->display.get_fifo_size = i85x_get_fifo_size;
         } else {
-                if (IS_I85X(dev))
-                        dev_priv->display.get_fifo_size = i85x_get_fifo_size;
-                else if (IS_845G(dev))
+                dev_priv->display.update_wm = i830_update_wm;
+                if (IS_845G(dev))
                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
                 else
                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
-                dev_priv->display.update_wm = i830_update_wm;
         }
 }