drm/i915/crt: Flush register prior to waiting for vblank.

If we don't flush the write then we can not be sure that the border
colour will have taken effect by the time we try to read it back.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

1 files changed, 1 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index c2982e48b61f..626279791b89 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -327,6 +327,7 @@ intel_crt_load_detect(struct drm_crtc *crtc, struct intel_encoder *intel_encoder
         if (IS_I9XX(dev)) {
                 uint32_t pipeconf = I915_READ(pipeconf_reg);
                 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
+                POSTING_READ(pipeconf_reg);
                 /* Wait for next Vblank to substitue
                  * border color for Color info */
                 intel_wait_for_vblank(dev, pipe);