diff options
author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2013-02-18 17:00:27 -0500 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-03-04 17:14:35 -0500 |
commit | e2debe919a859a350a542a361705a51e4567b6db (patch) | |
tree | 7ac8d43538b3b542dac0b0f9e44a48d0334c321f /drivers/gpu/drm/i915/i915_reg.h | |
parent | da1a62acd01c1fe09bc7019b36412f50a43d0e2d (diff) |
drm/i915: clarify confusion between SDVO and HDMI registers
Some HDMI registers can be used for SDVO, so saying "HDMIB" should be
the same as saying "SDVOB" for a given HW generation. This was not
true and led to confusions and even a regression.
Previously we had:
- SDVO{B,C} defined as the Gen3+ registers
- HDMI{B,C,D} and PCH_SDVOB defined as the PCH registers
But now:
- SDVO{B,C} became GEN3_SDVO{B,C} on SDVO code
- SDVO{B,C} became GEN4_HDMI{B,C} on HDMI code
- HDMI{B,C,D} became PCH_HDMI{B,C,D}
- PCH_SDVOB is still the same thing
v2: Rebase (v1 was sent in May 2012).
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 19 |
1 files changed, 9 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c6d482fdf89b..448e13c26c87 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -1681,8 +1681,9 @@ | |||
1681 | #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) | 1681 | #define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6) |
1682 | 1682 | ||
1683 | /* SDVO port control */ | 1683 | /* SDVO port control */ |
1684 | #define SDVOB 0x61140 | 1684 | #define GEN3_SDVOB 0x61140 |
1685 | #define SDVOC 0x61160 | 1685 | #define GEN3_SDVOC 0x61160 |
1686 | #define PCH_SDVOB 0xe1140 | ||
1686 | #define SDVO_ENABLE (1 << 31) | 1687 | #define SDVO_ENABLE (1 << 31) |
1687 | #define SDVO_PIPE_B_SELECT (1 << 30) | 1688 | #define SDVO_PIPE_B_SELECT (1 << 30) |
1688 | #define SDVO_STALL_SELECT (1 << 29) | 1689 | #define SDVO_STALL_SELECT (1 << 29) |
@@ -3982,8 +3983,12 @@ | |||
3982 | #define FDI_PLL_CTL_1 0xfe000 | 3983 | #define FDI_PLL_CTL_1 0xfe000 |
3983 | #define FDI_PLL_CTL_2 0xfe004 | 3984 | #define FDI_PLL_CTL_2 0xfe004 |
3984 | 3985 | ||
3985 | /* or SDVOB */ | 3986 | /* The same register may be used for SDVO or HDMI */ |
3986 | #define HDMIB 0xe1140 | 3987 | #define GEN4_HDMIB GEN3_SDVOB |
3988 | #define GEN4_HDMIC GEN3_SDVOC | ||
3989 | #define PCH_HDMIB PCH_SDVOB | ||
3990 | #define PCH_HDMIC 0xe1150 | ||
3991 | #define PCH_HDMID 0xe1160 | ||
3987 | #define PORT_ENABLE (1 << 31) | 3992 | #define PORT_ENABLE (1 << 31) |
3988 | #define TRANSCODER(pipe) ((pipe) << 30) | 3993 | #define TRANSCODER(pipe) ((pipe) << 30) |
3989 | #define TRANSCODER_CPT(pipe) ((pipe) << 29) | 3994 | #define TRANSCODER_CPT(pipe) ((pipe) << 29) |
@@ -4004,12 +4009,6 @@ | |||
4004 | #define HSYNC_ACTIVE_HIGH (1 << 3) | 4009 | #define HSYNC_ACTIVE_HIGH (1 << 3) |
4005 | #define PORT_DETECTED (1 << 2) | 4010 | #define PORT_DETECTED (1 << 2) |
4006 | 4011 | ||
4007 | /* PCH SDVOB multiplex with HDMIB */ | ||
4008 | #define PCH_SDVOB HDMIB | ||
4009 | |||
4010 | #define HDMIC 0xe1150 | ||
4011 | #define HDMID 0xe1160 | ||
4012 | |||
4013 | #define PCH_LVDS 0xe1180 | 4012 | #define PCH_LVDS 0xe1180 |
4014 | #define LVDS_DETECTED (1 << 1) | 4013 | #define LVDS_DETECTED (1 << 1) |
4015 | 4014 | ||