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authorChris Wilson <chris@chris-wilson.co.uk>2013-09-25 12:34:57 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-10-03 14:01:31 -0400
commitdd75fdc8c69587c91bd68a6ed7c726b5e70f9399 (patch)
tree79fdff479e1fe353dfa8b717e41ae6e7c1aa13fb /drivers/gpu/drm/i915/i915_reg.h
parentb29c19b645287f7062e17d70fa4e9781a01a5d88 (diff)
drm/i915: Tweak RPS thresholds to more aggressively downclock
After applying wait-boost we often find ourselves stuck at higher clocks than required. The current threshold value requires the GPU to be continuously and completely idle for 313ms before it is dropped by one bin. Conversely, we require the GPU to be busy for an average of 90% over a 84ms period before we upclock. So the current thresholds almost never downclock the GPU, and respond very slowly to sudden demands for more power. It is easy to observe that we currently lock into the wrong bin and both underperform in benchmarks and consume more power than optimal (just by repeating the task and measuring the different results). An alternative approach, as discussed in the bspec, is to use a continuous threshold for upclocking, and an average value for downclocking. This is good for quickly detecting and reacting to state changes within a frame, however it fails with the common throttling method of waiting upon the outstanding frame - at least it is difficult to choose a threshold that works well at 15,000fps and at 60fps. So continue to use average busy/idle loads to determine frequency change. v2: Use 3 power zones to keep frequencies low in steady-state mostly idle (e.g. scrolling, interactive 2D drawing), and frequencies high for demanding games. In between those end-states, we use a fast-reclocking algorithm to converge more quickly on the desired bin. v3: Bug fixes - make sure we reset adj after switching power zones. v4: Tune - drop the continuous busy thresholds as it prevents us from choosing the right frequency for glxgears style swap benchmarks. Instead the goal is to be able to find the right clocks irrespective of the wait-boost. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Kenneth Graunke <kenneth@whitecape.org> Cc: Stéphane Marchesin <stephane.marchesin@gmail.com> Cc: Owen Taylor <otaylor@redhat.com> Cc: "Meng, Mengmeng" <mengmeng.meng@intel.com> Cc: "Zhuang, Lena" <lena.zhuang@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 96fd2ce6aa02..daaabe788f21 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4687,7 +4687,7 @@
4687#define GEN6_RP_UP_IDLE_MIN (0x1<<3) 4687#define GEN6_RP_UP_IDLE_MIN (0x1<<3)
4688#define GEN6_RP_UP_BUSY_AVG (0x2<<3) 4688#define GEN6_RP_UP_BUSY_AVG (0x2<<3)
4689#define GEN6_RP_UP_BUSY_CONT (0x4<<3) 4689#define GEN6_RP_UP_BUSY_CONT (0x4<<3)
4690#define GEN7_RP_DOWN_IDLE_AVG (0x2<<0) 4690#define GEN6_RP_DOWN_IDLE_AVG (0x2<<0)
4691#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0) 4691#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
4692#define GEN6_RP_UP_THRESHOLD 0xA02C 4692#define GEN6_RP_UP_THRESHOLD 0xA02C
4693#define GEN6_RP_DOWN_THRESHOLD 0xA030 4693#define GEN6_RP_DOWN_THRESHOLD 0xA030