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authorEric Anholt <eric@anholt.net>2009-03-11 01:34:49 -0400
committerEric Anholt <eric@anholt.net>2009-03-11 14:02:06 -0400
commitdc529a4fe1ae4667c819437a94185e8581e1e680 (patch)
tree88933130acf93d8715b42c232aae8be369e1ed0e /drivers/gpu/drm/i915/i915_reg.h
parentd7619c4b9c95cc9a2e7f0f4f7ae21165ab5cb1e7 (diff)
drm/i915: fix 945 fence register writes for fence 8 and above.
The last 8 fence registers sit at a different offset, so when we went to set fence number 8 in the lower offset, we instead set PGETBL_CTL, and the GPU got all sorts of angry at us. fd.o bug #20567. Easily reproducible by running glxgears and killing it about 6 times. Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9d6539a868b3..90600d899413 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -184,6 +184,7 @@
184 * Fence registers 184 * Fence registers
185 */ 185 */
186#define FENCE_REG_830_0 0x2000 186#define FENCE_REG_830_0 0x2000
187#define FENCE_REG_945_8 0x3000
187#define I830_FENCE_START_MASK 0x07f80000 188#define I830_FENCE_START_MASK 0x07f80000
188#define I830_FENCE_TILING_Y_SHIFT 12 189#define I830_FENCE_TILING_Y_SHIFT 12
189#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) 190#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)