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authorLinus Torvalds <torvalds@linux-foundation.org>2012-03-22 16:08:22 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-03-22 16:08:22 -0400
commitbe53bfdb8088e9d1924199cc1a96e113756b1075 (patch)
tree8c65eb9d82ca4c0f11c17cfdc44d5263820b415b /drivers/gpu/drm/i915/i915_reg.h
parentb2094ef840697bc8ca5d17a83b7e30fad5f1e9fa (diff)
parent5466c7b1683a23dbbcfb7ee4a71c4f23886001c7 (diff)
Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux
Pull drm main changes from Dave Airlie: "This is the main drm pull request, I'm probably going to send two more smaller ones, will explain below. This contains a patch that is also in the fbdev tree, but it should be the same patch, it added an API for hot unplugging framebuffer devices, and I need that API for a new driver. It also contains some changes to the i2c tree which Jean has acked, and one change to moorestown platform stuff in x86. Highlights: - new drivers: UDL driver for USB displaylink devices, kms only, should support correct hotplug operations. - core: i2c speedups + better hotplug support, EDID overriding via firmware interface - allows user to load a firmware for a broken monitor/kvm from userspace, it even has documentation for it. - exynos: new HDMI audio + hdmi 1.4 + virtual output driver - gma500: code cleanup - radeon: cleanups, CS optimisations, streamout support and pageflip fix - nouveau: NVD9 displayport support + more reclocking work - i915: re-enabling GMBUS, finish gpu patch (might help hibernation who knows), missed irq fixes, stencil tiling fixes, interlaced support, aliasesd PPGTT support for SNB/IVB, swizzling for SNB/IVB, semaphore fixes As well as the usual bunch of cleanups and fixes all over the place. I've got two things I'd like to merge a bit later: a) AMD support for all their new radeonhd 7000 series GPU and APUs. AMD dropped this a bit late due to insane internal review processes, (please AMD just follow Intel and let open source guys ship stuff early) however I don't want to penalise people who own this hardware (since its been on sale for 3-4 months and GPU hw doesn't exactly have a lifetime in years) and consign them to using closed drivers for longer than necessary. The changes are well contained and just plug into the driver new gpu functionality so they should be fairly regression proof. I just want to give them a bit of a run on the hw AMD kindly sent me. b) drm prime/dma-buf interface code. This is just infrastructure code to expose the dma-buf stuff to drm drivers and to userspace. I'm not planning on pushing any driver support in this cycle (except maybe exynos), but I'd like to get the infrastructure code in so for the next cycle I can start getting the driver support into the individual drivers. We have started driver support for i915, nouveau and udl along with I think exynos and omap in staging. However this code relies on the dma-buf tree being pulled into your tree first since it needs the latest interfaces from that tree. I'll push to get that tree sent asap. (oh and any warnings you see in i915 are gcc's fault from what anyone can see)." Fix up trivial conflicts in arch/x86/platform/mrst/mrst.c due to the new msic_thermal_platform_data() thermal function being added next to the tc35876x_platform_data() i2c device function.. * 'drm-next' of git://people.freedesktop.org/~airlied/linux: (326 commits) drm/i915: use DDC_ADDR instead of hard-coding it drm/radeon: use DDC_ADDR instead of hard-coding it drm: remove unneeded redefinition of DDC_ADDR drm/exynos: added virtual display driver. drm: allow loading an EDID as firmware to override broken monitor drm/exynos: enable hdmi audio feature drm/exynos: add default pixel format for plane drm/exynos: cleanup exynos_hdmi.h drm/exynos: add is_local member in exynos_drm_subdrv struct drm/exynos: add subdrv open/close functions drm/exynos: remove module of exynos drm subdrv drm/exynos: release pending pageflip events when closed drm/exynos: added new funtion to get/put dma address. drm/exynos: update gem and buffer framework. drm/exynos: added mode_fixup feature and code clean. drm/exynos: add HDMI version 1.4 support drm/exynos: remove exynos_mixer.h gma500: Fix mmap frambuffer drm/radeon: Drop radeon_gem_object_(un)pin. drm/radeon: Restrict offset for legacy display engine. ...
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h132
1 files changed, 120 insertions, 12 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 558ac716a328..3886cf051bac 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -86,12 +86,45 @@
86#define GEN6_MBC_SNPCR_LOW (2<<21) 86#define GEN6_MBC_SNPCR_LOW (2<<21)
87#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ 87#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
88 88
89#define GEN6_MBCTL 0x0907c
90#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
91#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
92#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
93#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
94#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
95
89#define GEN6_GDRST 0x941c 96#define GEN6_GDRST 0x941c
90#define GEN6_GRDOM_FULL (1 << 0) 97#define GEN6_GRDOM_FULL (1 << 0)
91#define GEN6_GRDOM_RENDER (1 << 1) 98#define GEN6_GRDOM_RENDER (1 << 1)
92#define GEN6_GRDOM_MEDIA (1 << 2) 99#define GEN6_GRDOM_MEDIA (1 << 2)
93#define GEN6_GRDOM_BLT (1 << 3) 100#define GEN6_GRDOM_BLT (1 << 3)
94 101
102/* PPGTT stuff */
103#define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
104
105#define GEN6_PDE_VALID (1 << 0)
106#define GEN6_PDE_LARGE_PAGE (2 << 0) /* use 32kb pages */
107/* gen6+ has bit 11-4 for physical addr bit 39-32 */
108#define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
109
110#define GEN6_PTE_VALID (1 << 0)
111#define GEN6_PTE_UNCACHED (1 << 1)
112#define GEN6_PTE_CACHE_LLC (2 << 1)
113#define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
114#define GEN6_PTE_CACHE_BITS (3 << 1)
115#define GEN6_PTE_GFDT (1 << 3)
116#define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
117
118#define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
119#define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
120#define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
121#define PP_DIR_DCLV_2G 0xffffffff
122
123#define GAM_ECOCHK 0x4090
124#define ECOCHK_SNB_BIT (1<<10)
125#define ECOCHK_PPGTT_CACHE64B (0x3<<3)
126#define ECOCHK_PPGTT_CACHE4B (0x0<<3)
127
95/* VGA stuff */ 128/* VGA stuff */
96 129
97#define VGA_ST01_MDA 0x3ba 130#define VGA_ST01_MDA 0x3ba
@@ -295,6 +328,12 @@
295#define FENCE_REG_SANDYBRIDGE_0 0x100000 328#define FENCE_REG_SANDYBRIDGE_0 0x100000
296#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32 329#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
297 330
331/* control register for cpu gtt access */
332#define TILECTL 0x101000
333#define TILECTL_SWZCTL (1 << 0)
334#define TILECTL_TLB_PREFETCH_DIS (1 << 2)
335#define TILECTL_BACKSNOOP_DIS (1 << 3)
336
298/* 337/*
299 * Instruction and interrupt control regs 338 * Instruction and interrupt control regs
300 */ 339 */
@@ -318,7 +357,14 @@
318#define RING_MAX_IDLE(base) ((base)+0x54) 357#define RING_MAX_IDLE(base) ((base)+0x54)
319#define RING_HWS_PGA(base) ((base)+0x80) 358#define RING_HWS_PGA(base) ((base)+0x80)
320#define RING_HWS_PGA_GEN6(base) ((base)+0x2080) 359#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
360#define ARB_MODE 0x04030
361#define ARB_MODE_SWIZZLE_SNB (1<<4)
362#define ARB_MODE_SWIZZLE_IVB (1<<5)
363#define ARB_MODE_ENABLE(x) GFX_MODE_ENABLE(x)
364#define ARB_MODE_DISABLE(x) GFX_MODE_DISABLE(x)
321#define RENDER_HWS_PGA_GEN7 (0x04080) 365#define RENDER_HWS_PGA_GEN7 (0x04080)
366#define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
367#define DONE_REG 0x40b0
322#define BSD_HWS_PGA_GEN7 (0x04180) 368#define BSD_HWS_PGA_GEN7 (0x04180)
323#define BLT_HWS_PGA_GEN7 (0x04280) 369#define BLT_HWS_PGA_GEN7 (0x04280)
324#define RING_ACTHD(base) ((base)+0x74) 370#define RING_ACTHD(base) ((base)+0x74)
@@ -352,6 +398,12 @@
352#define IPEIR_I965 0x02064 398#define IPEIR_I965 0x02064
353#define IPEHR_I965 0x02068 399#define IPEHR_I965 0x02068
354#define INSTDONE_I965 0x0206c 400#define INSTDONE_I965 0x0206c
401#define RING_IPEIR(base) ((base)+0x64)
402#define RING_IPEHR(base) ((base)+0x68)
403#define RING_INSTDONE(base) ((base)+0x6c)
404#define RING_INSTPS(base) ((base)+0x70)
405#define RING_DMA_FADD(base) ((base)+0x78)
406#define RING_INSTPM(base) ((base)+0xc0)
355#define INSTPS 0x02070 /* 965+ only */ 407#define INSTPS 0x02070 /* 965+ only */
356#define INSTDONE1 0x0207c /* 965+ only */ 408#define INSTDONE1 0x0207c /* 965+ only */
357#define ACTHD_I965 0x02074 409#define ACTHD_I965 0x02074
@@ -365,14 +417,6 @@
365#define INSTDONE 0x02090 417#define INSTDONE 0x02090
366#define NOPID 0x02094 418#define NOPID 0x02094
367#define HWSTAM 0x02098 419#define HWSTAM 0x02098
368#define VCS_INSTDONE 0x1206C
369#define VCS_IPEIR 0x12064
370#define VCS_IPEHR 0x12068
371#define VCS_ACTHD 0x12074
372#define BCS_INSTDONE 0x2206C
373#define BCS_IPEIR 0x22064
374#define BCS_IPEHR 0x22068
375#define BCS_ACTHD 0x22074
376 420
377#define ERROR_GEN6 0x040a0 421#define ERROR_GEN6 0x040a0
378 422
@@ -391,10 +435,11 @@
391 435
392#define MI_MODE 0x0209c 436#define MI_MODE 0x0209c
393# define VS_TIMER_DISPATCH (1 << 6) 437# define VS_TIMER_DISPATCH (1 << 6)
394# define MI_FLUSH_ENABLE (1 << 11) 438# define MI_FLUSH_ENABLE (1 << 12)
395 439
396#define GFX_MODE 0x02520 440#define GFX_MODE 0x02520
397#define GFX_MODE_GEN7 0x0229c 441#define GFX_MODE_GEN7 0x0229c
442#define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
398#define GFX_RUN_LIST_ENABLE (1<<15) 443#define GFX_RUN_LIST_ENABLE (1<<15)
399#define GFX_TLB_INVALIDATE_ALWAYS (1<<13) 444#define GFX_TLB_INVALIDATE_ALWAYS (1<<13)
400#define GFX_SURFACE_FAULT_ENABLE (1<<12) 445#define GFX_SURFACE_FAULT_ENABLE (1<<12)
@@ -1037,6 +1082,29 @@
1037#define C0DRB3 0x10206 1082#define C0DRB3 0x10206
1038#define C1DRB3 0x10606 1083#define C1DRB3 0x10606
1039 1084
1085/** snb MCH registers for reading the DRAM channel configuration */
1086#define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004)
1087#define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008)
1088#define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C)
1089#define MAD_DIMM_ECC_MASK (0x3 << 24)
1090#define MAD_DIMM_ECC_OFF (0x0 << 24)
1091#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
1092#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
1093#define MAD_DIMM_ECC_ON (0x3 << 24)
1094#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
1095#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
1096#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
1097#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
1098#define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
1099#define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
1100#define MAD_DIMM_A_SELECT (0x1 << 16)
1101/* DIMM sizes are in multiples of 256mb. */
1102#define MAD_DIMM_B_SIZE_SHIFT 8
1103#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
1104#define MAD_DIMM_A_SIZE_SHIFT 0
1105#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
1106
1107
1040/* Clocking configuration register */ 1108/* Clocking configuration register */
1041#define CLKCFG 0x10c00 1109#define CLKCFG 0x10c00
1042#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */ 1110#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
@@ -1316,6 +1384,7 @@
1316#define _VSYNC_A 0x60014 1384#define _VSYNC_A 0x60014
1317#define _PIPEASRC 0x6001c 1385#define _PIPEASRC 0x6001c
1318#define _BCLRPAT_A 0x60020 1386#define _BCLRPAT_A 0x60020
1387#define _VSYNCSHIFT_A 0x60028
1319 1388
1320/* Pipe B timing regs */ 1389/* Pipe B timing regs */
1321#define _HTOTAL_B 0x61000 1390#define _HTOTAL_B 0x61000
@@ -1326,6 +1395,8 @@
1326#define _VSYNC_B 0x61014 1395#define _VSYNC_B 0x61014
1327#define _PIPEBSRC 0x6101c 1396#define _PIPEBSRC 0x6101c
1328#define _BCLRPAT_B 0x61020 1397#define _BCLRPAT_B 0x61020
1398#define _VSYNCSHIFT_B 0x61028
1399
1329 1400
1330#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B) 1401#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
1331#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B) 1402#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
@@ -1334,6 +1405,7 @@
1334#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B) 1405#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
1335#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B) 1406#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
1336#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) 1407#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
1408#define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
1337 1409
1338/* VGA port control */ 1410/* VGA port control */
1339#define ADPA 0x61100 1411#define ADPA 0x61100
@@ -2319,10 +2391,21 @@
2319#define PIPECONF_PALETTE 0 2391#define PIPECONF_PALETTE 0
2320#define PIPECONF_GAMMA (1<<24) 2392#define PIPECONF_GAMMA (1<<24)
2321#define PIPECONF_FORCE_BORDER (1<<25) 2393#define PIPECONF_FORCE_BORDER (1<<25)
2322#define PIPECONF_PROGRESSIVE (0 << 21)
2323#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
2324#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
2325#define PIPECONF_INTERLACE_MASK (7 << 21) 2394#define PIPECONF_INTERLACE_MASK (7 << 21)
2395/* Note that pre-gen3 does not support interlaced display directly. Panel
2396 * fitting must be disabled on pre-ilk for interlaced. */
2397#define PIPECONF_PROGRESSIVE (0 << 21)
2398#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
2399#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
2400#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
2401#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
2402/* Ironlake and later have a complete new set of values for interlaced. PFIT
2403 * means panel fitter required, PF means progressive fetch, DBL means power
2404 * saving pixel doubling. */
2405#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
2406#define PIPECONF_INTERLACED_ILK (3 << 21)
2407#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
2408#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
2326#define PIPECONF_CXSR_DOWNCLOCK (1<<16) 2409#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
2327#define PIPECONF_BPP_MASK (0x000000e0) 2410#define PIPECONF_BPP_MASK (0x000000e0)
2328#define PIPECONF_BPP_8 (0<<5) 2411#define PIPECONF_BPP_8 (0<<5)
@@ -3219,6 +3302,7 @@
3219#define _TRANS_VSYNC_A 0xe0014 3302#define _TRANS_VSYNC_A 0xe0014
3220#define TRANS_VSYNC_END_SHIFT 16 3303#define TRANS_VSYNC_END_SHIFT 16
3221#define TRANS_VSYNC_START_SHIFT 0 3304#define TRANS_VSYNC_START_SHIFT 0
3305#define _TRANS_VSYNCSHIFT_A 0xe0028
3222 3306
3223#define _TRANSA_DATA_M1 0xe0030 3307#define _TRANSA_DATA_M1 0xe0030
3224#define _TRANSA_DATA_N1 0xe0034 3308#define _TRANSA_DATA_N1 0xe0034
@@ -3249,6 +3333,7 @@
3249#define _TRANS_VTOTAL_B 0xe100c 3333#define _TRANS_VTOTAL_B 0xe100c
3250#define _TRANS_VBLANK_B 0xe1010 3334#define _TRANS_VBLANK_B 0xe1010
3251#define _TRANS_VSYNC_B 0xe1014 3335#define _TRANS_VSYNC_B 0xe1014
3336#define _TRANS_VSYNCSHIFT_B 0xe1028
3252 3337
3253#define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B) 3338#define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
3254#define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B) 3339#define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
@@ -3256,6 +3341,8 @@
3256#define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B) 3341#define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
3257#define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B) 3342#define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
3258#define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B) 3343#define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
3344#define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \
3345 _TRANS_VSYNCSHIFT_B)
3259 3346
3260#define _TRANSB_DATA_M1 0xe1030 3347#define _TRANSB_DATA_M1 0xe1030
3261#define _TRANSB_DATA_N1 0xe1034 3348#define _TRANSB_DATA_N1 0xe1034
@@ -3289,7 +3376,10 @@
3289#define TRANS_FSYNC_DELAY_HB4 (3<<27) 3376#define TRANS_FSYNC_DELAY_HB4 (3<<27)
3290#define TRANS_DP_AUDIO_ONLY (1<<26) 3377#define TRANS_DP_AUDIO_ONLY (1<<26)
3291#define TRANS_DP_VIDEO_AUDIO (0<<26) 3378#define TRANS_DP_VIDEO_AUDIO (0<<26)
3379#define TRANS_INTERLACE_MASK (7<<21)
3292#define TRANS_PROGRESSIVE (0<<21) 3380#define TRANS_PROGRESSIVE (0<<21)
3381#define TRANS_INTERLACED (3<<21)
3382#define TRANS_LEGACY_INTERLACED_ILK (2<<21)
3293#define TRANS_8BPC (0<<5) 3383#define TRANS_8BPC (0<<5)
3294#define TRANS_10BPC (1<<5) 3384#define TRANS_10BPC (1<<5)
3295#define TRANS_6BPC (2<<5) 3385#define TRANS_6BPC (2<<5)
@@ -3628,6 +3718,12 @@
3628#define ECOBUS 0xa180 3718#define ECOBUS 0xa180
3629#define FORCEWAKE_MT_ENABLE (1<<5) 3719#define FORCEWAKE_MT_ENABLE (1<<5)
3630 3720
3721#define GTFIFODBG 0x120000
3722#define GT_FIFO_CPU_ERROR_MASK 7
3723#define GT_FIFO_OVFERR (1<<2)
3724#define GT_FIFO_IAWRERR (1<<1)
3725#define GT_FIFO_IARDERR (1<<0)
3726
3631#define GT_FIFO_FREE_ENTRIES 0x120008 3727#define GT_FIFO_FREE_ENTRIES 0x120008
3632#define GT_FIFO_NUM_RESERVED_ENTRIES 20 3728#define GT_FIFO_NUM_RESERVED_ENTRIES 20
3633 3729
@@ -3757,4 +3853,16 @@
3757 */ 3853 */
3758#define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4) 3854#define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
3759 3855
3856#define IBX_AUD_CONFIG_A 0xe2000
3857#define CPT_AUD_CONFIG_A 0xe5000
3858#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
3859#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
3860#define AUD_CONFIG_UPPER_N_SHIFT 20
3861#define AUD_CONFIG_UPPER_N_VALUE (0xff << 20)
3862#define AUD_CONFIG_LOWER_N_SHIFT 4
3863#define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4)
3864#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
3865#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16)
3866#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
3867
3760#endif /* _I915_REG_H_ */ 3868#endif /* _I915_REG_H_ */