drm/i915: convert DDI_FUNC_CTL to transcoder

Because there's one instance of the register per CPU transcoder and
not per CPU pipe. This is another register that appeared for the first
time on Haswell, and even though its Haswell name is
PIPE_DDI_FUNC_CTL, it will be renamed to TRANS_DDI_FUNC_CTL, so let's
just use the new naming scheme before it confuses more people.

Notice that there's a big improvement on intel_ddi_get_hw_state due to
the new TRANSCODER_EDP.

V2: Also rename the register to TRANS_DDI_FUNC_CTL as suggested by
Damien Lespiau.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 32 insertions, 27 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 99cda88819c7..04705b62d4d0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4399,34 +4399,39 @@
 #define HSW_PWR_WELL_CTL6                       0x45414
 
 /* Per-pipe DDI Function Control */
-#define PIPE_DDI_FUNC_CTL_A             0x60400
-#define PIPE_DDI_FUNC_CTL_B             0x61400
-#define PIPE_DDI_FUNC_CTL_C             0x62400
-#define PIPE_DDI_FUNC_CTL_EDP           0x6F400
-#define DDI_FUNC_CTL(pipe) _PIPE(pipe, PIPE_DDI_FUNC_CTL_A, \
-                                       PIPE_DDI_FUNC_CTL_B)
-#define  PIPE_DDI_FUNC_ENABLE           (1<<31)
+#define TRANS_DDI_FUNC_CTL_A            0x60400
+#define TRANS_DDI_FUNC_CTL_B            0x61400
+#define TRANS_DDI_FUNC_CTL_C            0x62400
+#define TRANS_DDI_FUNC_CTL_EDP          0x6F400
+#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \
+                                                   TRANS_DDI_FUNC_CTL_B)
+#define  TRANS_DDI_FUNC_ENABLE          (1<<31)
 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
-#define  PIPE_DDI_PORT_MASK             (7<<28)
-#define  PIPE_DDI_SELECT_PORT(x)        ((x)<<28)
-#define  PIPE_DDI_PORT_NONE             (0<<28)
-#define  PIPE_DDI_MODE_SELECT_MASK      (7<<24)
-#define  PIPE_DDI_MODE_SELECT_HDMI      (0<<24)
-#define  PIPE_DDI_MODE_SELECT_DVI       (1<<24)
-#define  PIPE_DDI_MODE_SELECT_DP_SST    (2<<24)
-#define  PIPE_DDI_MODE_SELECT_DP_MST    (3<<24)
-#define  PIPE_DDI_MODE_SELECT_FDI       (4<<24)
-#define  PIPE_DDI_BPC_MASK              (7<<20)
-#define  PIPE_DDI_BPC_8                 (0<<20)
-#define  PIPE_DDI_BPC_10                (1<<20)
-#define  PIPE_DDI_BPC_6                 (2<<20)
-#define  PIPE_DDI_BPC_12                (3<<20)
-#define  PIPE_DDI_PVSYNC                (1<<17)
-#define  PIPE_DDI_PHSYNC                (1<<16)
-#define  PIPE_DDI_BFI_ENABLE            (1<<4)
-#define  PIPE_DDI_PORT_WIDTH_X1         (0<<1)
-#define  PIPE_DDI_PORT_WIDTH_X2         (1<<1)
-#define  PIPE_DDI_PORT_WIDTH_X4         (3<<1)
+#define  TRANS_DDI_PORT_MASK            (7<<28)
+#define  TRANS_DDI_SELECT_PORT(x)       ((x)<<28)
+#define  TRANS_DDI_PORT_NONE            (0<<28)
+#define  TRANS_DDI_MODE_SELECT_MASK     (7<<24)
+#define  TRANS_DDI_MODE_SELECT_HDMI     (0<<24)
+#define  TRANS_DDI_MODE_SELECT_DVI      (1<<24)
+#define  TRANS_DDI_MODE_SELECT_DP_SST   (2<<24)
+#define  TRANS_DDI_MODE_SELECT_DP_MST   (3<<24)
+#define  TRANS_DDI_MODE_SELECT_FDI      (4<<24)
+#define  TRANS_DDI_BPC_MASK             (7<<20)
+#define  TRANS_DDI_BPC_8                (0<<20)
+#define  TRANS_DDI_BPC_10               (1<<20)
+#define  TRANS_DDI_BPC_6                (2<<20)
+#define  TRANS_DDI_BPC_12               (3<<20)
+#define  TRANS_DDI_PVSYNC               (1<<17)
+#define  TRANS_DDI_PHSYNC               (1<<16)
+#define  TRANS_DDI_EDP_INPUT_MASK       (7<<12)
+#define  TRANS_DDI_EDP_INPUT_A_ON       (0<<12)
+#define  TRANS_DDI_EDP_INPUT_A_ONOFF    (4<<12)
+#define  TRANS_DDI_EDP_INPUT_B_ONOFF    (5<<12)
+#define  TRANS_DDI_EDP_INPUT_C_ONOFF    (6<<12)
+#define  TRANS_DDI_BFI_ENABLE           (1<<4)
+#define  TRANS_DDI_PORT_WIDTH_X1        (0<<1)
+#define  TRANS_DDI_PORT_WIDTH_X2        (1<<1)
+#define  TRANS_DDI_PORT_WIDTH_X4        (3<<1)
 
 /* DisplayPort Transport Control */
 #define DP_TP_CTL_A                     0x64040