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authorAntti Koskipaa <antti.koskipaa@linux.intel.com>2014-02-04 07:22:24 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-02-04 18:46:08 -0500
commita57c774ab2b849b9f53ec01308186355aa4227e5 (patch)
tree74aa11dd570fb82c935f5d1559e14b2417fc4648 /drivers/gpu/drm/i915/i915_reg.h
parent8c99e57d3926959dd940e834da6fa707601ba7e5 (diff)
drm/i915: Reorganize display pipe register accesses
RFCv2: Reorganize array indexing so that full offsets can be used as is. It makes grepping for registers in i915_reg.h much easier. Also move offset arrays to intel_device_info. v1: Fixed offsets for VLV, proper eDP handling v2: Fixed BCLRPAT, PIPESRC, PIPECONF and DSP* macros. v3: Added EDP pipe comment, removed redundant offset arrays for MSA_MISC and DDI_FUNC_CTL. v4: Rename patch and report object size increase. v5: Change location of commas, add PIPE_EDP into enum pipe v6: Insert PIPE_EDP_OFFSET into pipe offset array v7: Set I915_MAX_PIPES back to 3, change more registers accessors to use the new macros, get rid of _PIPE_INC and add dev_priv as a parameter where required by the new macros. Upcoming hardware will not have the various display pipe register ranges evenly spaced in memory. Change register address calculations into array lookups. Tested on SNB, VLV, IVB, Gen2 and HSW w/eDP. I left the UMS cruft untouched. Size differences: text data bss dec hex filename 596431 4634 56 601121 92c21 i915.ko (new) 593199 4634 56 597889 91f81 i915.ko (old) Signed-off-by: Antti Koskipaa <antti.koskipaa@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h284
1 files changed, 159 insertions, 125 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9d0f4f7bbe6a..f73a49dd1a98 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -26,7 +26,6 @@
26#define _I915_REG_H_ 26#define _I915_REG_H_
27 27
28#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) 28#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
29#define _PIPE_INC(pipe, base, inc) ((base) + (pipe)*(inc))
30#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a))) 29#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
31 30
32#define _PORT(port, a, b) ((a) + (port)*((b)-(a))) 31#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
@@ -1203,6 +1202,10 @@
1203/* 1202/*
1204 * Clock control & power management 1203 * Clock control & power management
1205 */ 1204 */
1205#define DPLL_A_OFFSET 0x6014
1206#define DPLL_B_OFFSET 0x6018
1207#define DPLL(pipe) (dev_priv->info->dpll_offsets[pipe] + \
1208 dev_priv->info->display_mmio_offset)
1206 1209
1207#define VGA0 0x6000 1210#define VGA0 0x6000
1208#define VGA1 0x6004 1211#define VGA1 0x6004
@@ -1215,9 +1218,6 @@
1215#define VGA1_PD_P1_DIV_2 (1 << 13) 1218#define VGA1_PD_P1_DIV_2 (1 << 13)
1216#define VGA1_PD_P1_SHIFT 8 1219#define VGA1_PD_P1_SHIFT 8
1217#define VGA1_PD_P1_MASK (0x1f << 8) 1220#define VGA1_PD_P1_MASK (0x1f << 8)
1218#define _DPLL_A (dev_priv->info->display_mmio_offset + 0x6014)
1219#define _DPLL_B (dev_priv->info->display_mmio_offset + 0x6018)
1220#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
1221#define DPLL_VCO_ENABLE (1 << 31) 1221#define DPLL_VCO_ENABLE (1 << 31)
1222#define DPLL_SDVO_HIGH_SPEED (1 << 30) 1222#define DPLL_SDVO_HIGH_SPEED (1 << 30)
1223#define DPLL_DVO_2X_MODE (1 << 30) 1223#define DPLL_DVO_2X_MODE (1 << 30)
@@ -1279,7 +1279,12 @@
1279#define SDVO_MULTIPLIER_MASK 0x000000ff 1279#define SDVO_MULTIPLIER_MASK 0x000000ff
1280#define SDVO_MULTIPLIER_SHIFT_HIRES 4 1280#define SDVO_MULTIPLIER_SHIFT_HIRES 4
1281#define SDVO_MULTIPLIER_SHIFT_VGA 0 1281#define SDVO_MULTIPLIER_SHIFT_VGA 0
1282#define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c) /* 965+ only */ 1282
1283#define DPLL_A_MD_OFFSET 0x601c /* 965+ only */
1284#define DPLL_B_MD_OFFSET 0x6020 /* 965+ only */
1285#define DPLL_MD(pipe) (dev_priv->info->dpll_md_offsets[pipe] + \
1286 dev_priv->info->display_mmio_offset)
1287
1283/* 1288/*
1284 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 1289 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
1285 * 1290 *
@@ -1316,8 +1321,6 @@
1316 */ 1321 */
1317#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 1322#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
1318#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 1323#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
1319#define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020) /* 965+ only */
1320#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
1321 1324
1322#define _FPA0 0x06040 1325#define _FPA0 0x06040
1323#define _FPA1 0x06044 1326#define _FPA1 0x06044
@@ -1473,10 +1476,10 @@
1473/* 1476/*
1474 * Palette regs 1477 * Palette regs
1475 */ 1478 */
1476 1479#define PALETTE_A_OFFSET 0xa000
1477#define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000) 1480#define PALETTE_B_OFFSET 0xa800
1478#define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800) 1481#define PALETTE(pipe) (dev_priv->info->palette_offsets[pipe] + \
1479#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B) 1482 dev_priv->info->display_mmio_offset)
1480 1483
1481/* MCH MMIO space */ 1484/* MCH MMIO space */
1482 1485
@@ -1863,7 +1866,7 @@
1863 */ 1866 */
1864 1867
1865/* Pipe A CRC regs */ 1868/* Pipe A CRC regs */
1866#define _PIPE_CRC_CTL_A (dev_priv->info->display_mmio_offset + 0x60050) 1869#define _PIPE_CRC_CTL_A 0x60050
1867#define PIPE_CRC_ENABLE (1 << 31) 1870#define PIPE_CRC_ENABLE (1 << 31)
1868/* ivb+ source selection */ 1871/* ivb+ source selection */
1869#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29) 1872#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
@@ -1903,11 +1906,11 @@
1903#define _PIPE_CRC_RES_4_A_IVB 0x60070 1906#define _PIPE_CRC_RES_4_A_IVB 0x60070
1904#define _PIPE_CRC_RES_5_A_IVB 0x60074 1907#define _PIPE_CRC_RES_5_A_IVB 0x60074
1905 1908
1906#define _PIPE_CRC_RES_RED_A (dev_priv->info->display_mmio_offset + 0x60060) 1909#define _PIPE_CRC_RES_RED_A 0x60060
1907#define _PIPE_CRC_RES_GREEN_A (dev_priv->info->display_mmio_offset + 0x60064) 1910#define _PIPE_CRC_RES_GREEN_A 0x60064
1908#define _PIPE_CRC_RES_BLUE_A (dev_priv->info->display_mmio_offset + 0x60068) 1911#define _PIPE_CRC_RES_BLUE_A 0x60068
1909#define _PIPE_CRC_RES_RES1_A_I915 (dev_priv->info->display_mmio_offset + 0x6006c) 1912#define _PIPE_CRC_RES_RES1_A_I915 0x6006c
1910#define _PIPE_CRC_RES_RES2_A_G4X (dev_priv->info->display_mmio_offset + 0x60080) 1913#define _PIPE_CRC_RES_RES2_A_G4X 0x60080
1911 1914
1912/* Pipe B CRC regs */ 1915/* Pipe B CRC regs */
1913#define _PIPE_CRC_RES_1_B_IVB 0x61064 1916#define _PIPE_CRC_RES_1_B_IVB 0x61064
@@ -1916,59 +1919,69 @@
1916#define _PIPE_CRC_RES_4_B_IVB 0x61070 1919#define _PIPE_CRC_RES_4_B_IVB 0x61070
1917#define _PIPE_CRC_RES_5_B_IVB 0x61074 1920#define _PIPE_CRC_RES_5_B_IVB 0x61074
1918 1921
1919#define PIPE_CRC_CTL(pipe) _PIPE_INC(pipe, _PIPE_CRC_CTL_A, 0x01000) 1922#define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A)
1920#define PIPE_CRC_RES_1_IVB(pipe) \ 1923#define PIPE_CRC_RES_1_IVB(pipe) \
1921 _PIPE(pipe, _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB) 1924 _TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB)
1922#define PIPE_CRC_RES_2_IVB(pipe) \ 1925#define PIPE_CRC_RES_2_IVB(pipe) \
1923 _PIPE(pipe, _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB) 1926 _TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB)
1924#define PIPE_CRC_RES_3_IVB(pipe) \ 1927#define PIPE_CRC_RES_3_IVB(pipe) \
1925 _PIPE(pipe, _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB) 1928 _TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB)
1926#define PIPE_CRC_RES_4_IVB(pipe) \ 1929#define PIPE_CRC_RES_4_IVB(pipe) \
1927 _PIPE(pipe, _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB) 1930 _TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB)
1928#define PIPE_CRC_RES_5_IVB(pipe) \ 1931#define PIPE_CRC_RES_5_IVB(pipe) \
1929 _PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB) 1932 _TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB)
1930 1933
1931#define PIPE_CRC_RES_RED(pipe) \ 1934#define PIPE_CRC_RES_RED(pipe) \
1932 _PIPE_INC(pipe, _PIPE_CRC_RES_RED_A, 0x01000) 1935 _TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A)
1933#define PIPE_CRC_RES_GREEN(pipe) \ 1936#define PIPE_CRC_RES_GREEN(pipe) \
1934 _PIPE_INC(pipe, _PIPE_CRC_RES_GREEN_A, 0x01000) 1937 _TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A)
1935#define PIPE_CRC_RES_BLUE(pipe) \ 1938#define PIPE_CRC_RES_BLUE(pipe) \
1936 _PIPE_INC(pipe, _PIPE_CRC_RES_BLUE_A, 0x01000) 1939 _TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A)
1937#define PIPE_CRC_RES_RES1_I915(pipe) \ 1940#define PIPE_CRC_RES_RES1_I915(pipe) \
1938 _PIPE_INC(pipe, _PIPE_CRC_RES_RES1_A_I915, 0x01000) 1941 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915)
1939#define PIPE_CRC_RES_RES2_G4X(pipe) \ 1942#define PIPE_CRC_RES_RES2_G4X(pipe) \
1940 _PIPE_INC(pipe, _PIPE_CRC_RES_RES2_A_G4X, 0x01000) 1943 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
1941 1944
1942/* Pipe A timing regs */ 1945/* Pipe A timing regs */
1943#define _HTOTAL_A (dev_priv->info->display_mmio_offset + 0x60000) 1946#define _HTOTAL_A 0x60000
1944#define _HBLANK_A (dev_priv->info->display_mmio_offset + 0x60004) 1947#define _HBLANK_A 0x60004
1945#define _HSYNC_A (dev_priv->info->display_mmio_offset + 0x60008) 1948#define _HSYNC_A 0x60008
1946#define _VTOTAL_A (dev_priv->info->display_mmio_offset + 0x6000c) 1949#define _VTOTAL_A 0x6000c
1947#define _VBLANK_A (dev_priv->info->display_mmio_offset + 0x60010) 1950#define _VBLANK_A 0x60010
1948#define _VSYNC_A (dev_priv->info->display_mmio_offset + 0x60014) 1951#define _VSYNC_A 0x60014
1949#define _PIPEASRC (dev_priv->info->display_mmio_offset + 0x6001c) 1952#define _PIPEASRC 0x6001c
1950#define _BCLRPAT_A (dev_priv->info->display_mmio_offset + 0x60020) 1953#define _BCLRPAT_A 0x60020
1951#define _VSYNCSHIFT_A (dev_priv->info->display_mmio_offset + 0x60028) 1954#define _VSYNCSHIFT_A 0x60028
1952 1955
1953/* Pipe B timing regs */ 1956/* Pipe B timing regs */
1954#define _HTOTAL_B (dev_priv->info->display_mmio_offset + 0x61000) 1957#define _HTOTAL_B 0x61000
1955#define _HBLANK_B (dev_priv->info->display_mmio_offset + 0x61004) 1958#define _HBLANK_B 0x61004
1956#define _HSYNC_B (dev_priv->info->display_mmio_offset + 0x61008) 1959#define _HSYNC_B 0x61008
1957#define _VTOTAL_B (dev_priv->info->display_mmio_offset + 0x6100c) 1960#define _VTOTAL_B 0x6100c
1958#define _VBLANK_B (dev_priv->info->display_mmio_offset + 0x61010) 1961#define _VBLANK_B 0x61010
1959#define _VSYNC_B (dev_priv->info->display_mmio_offset + 0x61014) 1962#define _VSYNC_B 0x61014
1960#define _PIPEBSRC (dev_priv->info->display_mmio_offset + 0x6101c) 1963#define _PIPEBSRC 0x6101c
1961#define _BCLRPAT_B (dev_priv->info->display_mmio_offset + 0x61020) 1964#define _BCLRPAT_B 0x61020
1962#define _VSYNCSHIFT_B (dev_priv->info->display_mmio_offset + 0x61028) 1965#define _VSYNCSHIFT_B 0x61028
1963 1966
1964#define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B) 1967#define TRANSCODER_A_OFFSET 0x60000
1965#define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B) 1968#define TRANSCODER_B_OFFSET 0x61000
1966#define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B) 1969#define TRANSCODER_C_OFFSET 0x62000
1967#define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B) 1970#define TRANSCODER_EDP_OFFSET 0x6f000
1968#define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B) 1971
1969#define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B) 1972#define _TRANSCODER2(pipe, reg) (dev_priv->info->trans_offsets[(pipe)] - \
1970#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) 1973 dev_priv->info->trans_offsets[TRANSCODER_A] + (reg) + \
1971#define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B) 1974 dev_priv->info->display_mmio_offset)
1975
1976#define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A)
1977#define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A)
1978#define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A)
1979#define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A)
1980#define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A)
1981#define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A)
1982#define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A)
1983#define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)
1984#define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
1972 1985
1973/* HSW+ eDP PSR registers */ 1986/* HSW+ eDP PSR registers */
1974#define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800) 1987#define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
@@ -3179,10 +3192,10 @@
3179/* Display & cursor control */ 3192/* Display & cursor control */
3180 3193
3181/* Pipe A */ 3194/* Pipe A */
3182#define _PIPEADSL (dev_priv->info->display_mmio_offset + 0x70000) 3195#define _PIPEADSL 0x70000
3183#define DSL_LINEMASK_GEN2 0x00000fff 3196#define DSL_LINEMASK_GEN2 0x00000fff
3184#define DSL_LINEMASK_GEN3 0x00001fff 3197#define DSL_LINEMASK_GEN3 0x00001fff
3185#define _PIPEACONF (dev_priv->info->display_mmio_offset + 0x70008) 3198#define _PIPEACONF 0x70008
3186#define PIPECONF_ENABLE (1<<31) 3199#define PIPECONF_ENABLE (1<<31)
3187#define PIPECONF_DISABLE 0 3200#define PIPECONF_DISABLE 0
3188#define PIPECONF_DOUBLE_WIDE (1<<30) 3201#define PIPECONF_DOUBLE_WIDE (1<<30)
@@ -3225,7 +3238,7 @@
3225#define PIPECONF_DITHER_TYPE_ST1 (1<<2) 3238#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
3226#define PIPECONF_DITHER_TYPE_ST2 (2<<2) 3239#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
3227#define PIPECONF_DITHER_TYPE_TEMP (3<<2) 3240#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
3228#define _PIPEASTAT (dev_priv->info->display_mmio_offset + 0x70024) 3241#define _PIPEASTAT 0x70024
3229#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31) 3242#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
3230#define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30) 3243#define SPRITE1_FLIPDONE_INT_EN_VLV (1UL<<30)
3231#define PIPE_CRC_ERROR_ENABLE (1UL<<29) 3244#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
@@ -3263,12 +3276,26 @@
3263#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 3276#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
3264#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 3277#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
3265 3278
3266#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC) 3279#define PIPE_A_OFFSET 0x70000
3267#define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF) 3280#define PIPE_B_OFFSET 0x71000
3268#define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL) 3281#define PIPE_C_OFFSET 0x72000
3269#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH) 3282/*
3270#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL) 3283 * There's actually no pipe EDP. Some pipe registers have
3271#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT) 3284 * simply shifted from the pipe to the transcoder, while
3285 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
3286 * to access such registers in transcoder EDP.
3287 */
3288#define PIPE_EDP_OFFSET 0x7f000
3289
3290#define _PIPE2(pipe, reg) (dev_priv->info->pipe_offsets[pipe] - \
3291 dev_priv->info->pipe_offsets[PIPE_A] + (reg) + \
3292 dev_priv->info->display_mmio_offset)
3293
3294#define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF)
3295#define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL)
3296#define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH)
3297#define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL)
3298#define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT)
3272 3299
3273#define _PIPE_MISC_A 0x70030 3300#define _PIPE_MISC_A 0x70030
3274#define _PIPE_MISC_B 0x71030 3301#define _PIPE_MISC_B 0x71030
@@ -3280,7 +3307,7 @@
3280#define PIPEMISC_DITHER_ENABLE (1<<4) 3307#define PIPEMISC_DITHER_ENABLE (1<<4)
3281#define PIPEMISC_DITHER_TYPE_MASK (3<<2) 3308#define PIPEMISC_DITHER_TYPE_MASK (3<<2)
3282#define PIPEMISC_DITHER_TYPE_SP (0<<2) 3309#define PIPEMISC_DITHER_TYPE_SP (0<<2)
3283#define PIPEMISC(pipe) _PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B) 3310#define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A)
3284 3311
3285#define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028) 3312#define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028)
3286#define PIPEB_LINE_COMPARE_INT_EN (1<<29) 3313#define PIPEB_LINE_COMPARE_INT_EN (1<<29)
@@ -3521,7 +3548,7 @@
3521#define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB) 3548#define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
3522 3549
3523/* Display A control */ 3550/* Display A control */
3524#define _DSPACNTR (dev_priv->info->display_mmio_offset + 0x70180) 3551#define _DSPACNTR 0x70180
3525#define DISPLAY_PLANE_ENABLE (1<<31) 3552#define DISPLAY_PLANE_ENABLE (1<<31)
3526#define DISPLAY_PLANE_DISABLE 0 3553#define DISPLAY_PLANE_DISABLE 0
3527#define DISPPLANE_GAMMA_ENABLE (1<<30) 3554#define DISPPLANE_GAMMA_ENABLE (1<<30)
@@ -3555,25 +3582,25 @@
3555#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 3582#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
3556#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */ 3583#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
3557#define DISPPLANE_TILED (1<<10) 3584#define DISPPLANE_TILED (1<<10)
3558#define _DSPAADDR (dev_priv->info->display_mmio_offset + 0x70184) 3585#define _DSPAADDR 0x70184
3559#define _DSPASTRIDE (dev_priv->info->display_mmio_offset + 0x70188) 3586#define _DSPASTRIDE 0x70188
3560#define _DSPAPOS (dev_priv->info->display_mmio_offset + 0x7018C) /* reserved */ 3587#define _DSPAPOS 0x7018C /* reserved */
3561#define _DSPASIZE (dev_priv->info->display_mmio_offset + 0x70190) 3588#define _DSPASIZE 0x70190
3562#define _DSPASURF (dev_priv->info->display_mmio_offset + 0x7019C) /* 965+ only */ 3589#define _DSPASURF 0x7019C /* 965+ only */
3563#define _DSPATILEOFF (dev_priv->info->display_mmio_offset + 0x701A4) /* 965+ only */ 3590#define _DSPATILEOFF 0x701A4 /* 965+ only */
3564#define _DSPAOFFSET (dev_priv->info->display_mmio_offset + 0x701A4) /* HSW */ 3591#define _DSPAOFFSET 0x701A4 /* HSW */
3565#define _DSPASURFLIVE (dev_priv->info->display_mmio_offset + 0x701AC) 3592#define _DSPASURFLIVE 0x701AC
3566 3593
3567#define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR) 3594#define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR)
3568#define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR) 3595#define DSPADDR(plane) _PIPE2(plane, _DSPAADDR)
3569#define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE) 3596#define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE)
3570#define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS) 3597#define DSPPOS(plane) _PIPE2(plane, _DSPAPOS)
3571#define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE) 3598#define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE)
3572#define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) 3599#define DSPSURF(plane) _PIPE2(plane, _DSPASURF)
3573#define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) 3600#define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF)
3574#define DSPLINOFF(plane) DSPADDR(plane) 3601#define DSPLINOFF(plane) DSPADDR(plane)
3575#define DSPOFFSET(plane) _PIPE(plane, _DSPAOFFSET, _DSPBOFFSET) 3602#define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)
3576#define DSPSURFLIVE(plane) _PIPE(plane, _DSPASURFLIVE, _DSPBSURFLIVE) 3603#define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)
3577 3604
3578/* Display/Sprite base address macros */ 3605/* Display/Sprite base address macros */
3579#define DISP_BASEADDR_MASK (0xfffff000) 3606#define DISP_BASEADDR_MASK (0xfffff000)
@@ -3867,48 +3894,45 @@
3867#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff 3894#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
3868 3895
3869 3896
3870#define _PIPEA_DATA_M1 (dev_priv->info->display_mmio_offset + 0x60030) 3897#define _PIPEA_DATA_M1 0x60030
3871#define PIPE_DATA_M1_OFFSET 0 3898#define PIPE_DATA_M1_OFFSET 0
3872#define _PIPEA_DATA_N1 (dev_priv->info->display_mmio_offset + 0x60034) 3899#define _PIPEA_DATA_N1 0x60034
3873#define PIPE_DATA_N1_OFFSET 0 3900#define PIPE_DATA_N1_OFFSET 0
3874 3901
3875#define _PIPEA_DATA_M2 (dev_priv->info->display_mmio_offset + 0x60038) 3902#define _PIPEA_DATA_M2 0x60038
3876#define PIPE_DATA_M2_OFFSET 0 3903#define PIPE_DATA_M2_OFFSET 0
3877#define _PIPEA_DATA_N2 (dev_priv->info->display_mmio_offset + 0x6003c) 3904#define _PIPEA_DATA_N2 0x6003c
3878#define PIPE_DATA_N2_OFFSET 0 3905#define PIPE_DATA_N2_OFFSET 0
3879 3906
3880#define _PIPEA_LINK_M1 (dev_priv->info->display_mmio_offset + 0x60040) 3907#define _PIPEA_LINK_M1 0x60040
3881#define PIPE_LINK_M1_OFFSET 0 3908#define PIPE_LINK_M1_OFFSET 0
3882#define _PIPEA_LINK_N1 (dev_priv->info->display_mmio_offset + 0x60044) 3909#define _PIPEA_LINK_N1 0x60044
3883#define PIPE_LINK_N1_OFFSET 0 3910#define PIPE_LINK_N1_OFFSET 0
3884 3911
3885#define _PIPEA_LINK_M2 (dev_priv->info->display_mmio_offset + 0x60048) 3912#define _PIPEA_LINK_M2 0x60048
3886#define PIPE_LINK_M2_OFFSET 0 3913#define PIPE_LINK_M2_OFFSET 0
3887#define _PIPEA_LINK_N2 (dev_priv->info->display_mmio_offset + 0x6004c) 3914#define _PIPEA_LINK_N2 0x6004c
3888#define PIPE_LINK_N2_OFFSET 0 3915#define PIPE_LINK_N2_OFFSET 0
3889 3916
3890/* PIPEB timing regs are same start from 0x61000 */ 3917/* PIPEB timing regs are same start from 0x61000 */
3891 3918
3892#define _PIPEB_DATA_M1 (dev_priv->info->display_mmio_offset + 0x61030) 3919#define _PIPEB_DATA_M1 0x61030
3893#define _PIPEB_DATA_N1 (dev_priv->info->display_mmio_offset + 0x61034) 3920#define _PIPEB_DATA_N1 0x61034
3894 3921#define _PIPEB_DATA_M2 0x61038
3895#define _PIPEB_DATA_M2 (dev_priv->info->display_mmio_offset + 0x61038) 3922#define _PIPEB_DATA_N2 0x6103c
3896#define _PIPEB_DATA_N2 (dev_priv->info->display_mmio_offset + 0x6103c) 3923#define _PIPEB_LINK_M1 0x61040
3897 3924#define _PIPEB_LINK_N1 0x61044
3898#define _PIPEB_LINK_M1 (dev_priv->info->display_mmio_offset + 0x61040) 3925#define _PIPEB_LINK_M2 0x61048
3899#define _PIPEB_LINK_N1 (dev_priv->info->display_mmio_offset + 0x61044) 3926#define _PIPEB_LINK_N2 0x6104c
3900 3927
3901#define _PIPEB_LINK_M2 (dev_priv->info->display_mmio_offset + 0x61048) 3928#define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1)
3902#define _PIPEB_LINK_N2 (dev_priv->info->display_mmio_offset + 0x6104c) 3929#define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1)
3903 3930#define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2)
3904#define PIPE_DATA_M1(tran) _TRANSCODER(tran, _PIPEA_DATA_M1, _PIPEB_DATA_M1) 3931#define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2)
3905#define PIPE_DATA_N1(tran) _TRANSCODER(tran, _PIPEA_DATA_N1, _PIPEB_DATA_N1) 3932#define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1)
3906#define PIPE_DATA_M2(tran) _TRANSCODER(tran, _PIPEA_DATA_M2, _PIPEB_DATA_M2) 3933#define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1)
3907#define PIPE_DATA_N2(tran) _TRANSCODER(tran, _PIPEA_DATA_N2, _PIPEB_DATA_N2) 3934#define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2)
3908#define PIPE_LINK_M1(tran) _TRANSCODER(tran, _PIPEA_LINK_M1, _PIPEB_LINK_M1) 3935#define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2)
3909#define PIPE_LINK_N1(tran) _TRANSCODER(tran, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
3910#define PIPE_LINK_M2(tran) _TRANSCODER(tran, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
3911#define PIPE_LINK_N2(tran) _TRANSCODER(tran, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
3912 3936
3913/* CPU panel fitter */ 3937/* CPU panel fitter */
3914/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ 3938/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
@@ -4442,24 +4466,24 @@
4442#define HSW_VIDEO_DIP_GCP_B 0x61210 4466#define HSW_VIDEO_DIP_GCP_B 0x61210
4443 4467
4444#define HSW_TVIDEO_DIP_CTL(trans) \ 4468#define HSW_TVIDEO_DIP_CTL(trans) \
4445 _TRANSCODER(trans, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B) 4469 _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A)
4446#define HSW_TVIDEO_DIP_AVI_DATA(trans) \ 4470#define HSW_TVIDEO_DIP_AVI_DATA(trans) \
4447 _TRANSCODER(trans, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B) 4471 _TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A)
4448#define HSW_TVIDEO_DIP_VS_DATA(trans) \ 4472#define HSW_TVIDEO_DIP_VS_DATA(trans) \
4449 _TRANSCODER(trans, HSW_VIDEO_DIP_VS_DATA_A, HSW_VIDEO_DIP_VS_DATA_B) 4473 _TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A)
4450#define HSW_TVIDEO_DIP_SPD_DATA(trans) \ 4474#define HSW_TVIDEO_DIP_SPD_DATA(trans) \
4451 _TRANSCODER(trans, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B) 4475 _TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A)
4452#define HSW_TVIDEO_DIP_GCP(trans) \ 4476#define HSW_TVIDEO_DIP_GCP(trans) \
4453 _TRANSCODER(trans, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B) 4477 _TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A)
4454#define HSW_TVIDEO_DIP_VSC_DATA(trans) \ 4478#define HSW_TVIDEO_DIP_VSC_DATA(trans) \
4455 _TRANSCODER(trans, HSW_VIDEO_DIP_VSC_DATA_A, HSW_VIDEO_DIP_VSC_DATA_B) 4479 _TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A)
4456 4480
4457#define HSW_STEREO_3D_CTL_A 0x70020 4481#define HSW_STEREO_3D_CTL_A 0x70020
4458#define S3D_ENABLE (1<<31) 4482#define S3D_ENABLE (1<<31)
4459#define HSW_STEREO_3D_CTL_B 0x71020 4483#define HSW_STEREO_3D_CTL_B 0x71020
4460 4484
4461#define HSW_STEREO_3D_CTL(trans) \ 4485#define HSW_STEREO_3D_CTL(trans) \
4462 _TRANSCODER(trans, HSW_STEREO_3D_CTL_A, HSW_STEREO_3D_CTL_A) 4486 _PIPE2(trans, HSW_STEREO_3D_CTL_A)
4463 4487
4464#define _PCH_TRANS_HTOTAL_B 0xe1000 4488#define _PCH_TRANS_HTOTAL_B 0xe1000
4465#define _PCH_TRANS_HBLANK_B 0xe1004 4489#define _PCH_TRANS_HBLANK_B 0xe1004
@@ -5188,8 +5212,8 @@
5188#define TRANS_DDI_FUNC_CTL_B 0x61400 5212#define TRANS_DDI_FUNC_CTL_B 0x61400
5189#define TRANS_DDI_FUNC_CTL_C 0x62400 5213#define TRANS_DDI_FUNC_CTL_C 0x62400
5190#define TRANS_DDI_FUNC_CTL_EDP 0x6F400 5214#define TRANS_DDI_FUNC_CTL_EDP 0x6F400
5191#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \ 5215#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A)
5192 TRANS_DDI_FUNC_CTL_B) 5216
5193#define TRANS_DDI_FUNC_ENABLE (1<<31) 5217#define TRANS_DDI_FUNC_ENABLE (1<<31)
5194/* Those bits are ignored by pipe EDP since it can only connect to DDI A */ 5218/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
5195#define TRANS_DDI_PORT_MASK (7<<28) 5219#define TRANS_DDI_PORT_MASK (7<<28)
@@ -5366,10 +5390,12 @@
5366#define TRANS_CLK_SEL_DISABLED (0x0<<29) 5390#define TRANS_CLK_SEL_DISABLED (0x0<<29)
5367#define TRANS_CLK_SEL_PORT(x) ((x+1)<<29) 5391#define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)
5368 5392
5369#define _TRANSA_MSA_MISC 0x60410 5393#define TRANSA_MSA_MISC 0x60410
5370#define _TRANSB_MSA_MISC 0x61410 5394#define TRANSB_MSA_MISC 0x61410
5371#define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \ 5395#define TRANSC_MSA_MISC 0x62410
5372 _TRANSB_MSA_MISC) 5396#define TRANS_EDP_MSA_MISC 0x6f410
5397#define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC)
5398
5373#define TRANS_MSA_SYNC_CLK (1<<0) 5399#define TRANS_MSA_SYNC_CLK (1<<0)
5374#define TRANS_MSA_6_BPC (0<<5) 5400#define TRANS_MSA_6_BPC (0<<5)
5375#define TRANS_MSA_8_BPC (1<<5) 5401#define TRANS_MSA_8_BPC (1<<5)
@@ -5877,4 +5903,12 @@
5877#define MIPI_READ_DATA_VALID(pipe) _PIPE(pipe, _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID) 5903#define MIPI_READ_DATA_VALID(pipe) _PIPE(pipe, _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID)
5878#define READ_DATA_VALID(n) (1 << (n)) 5904#define READ_DATA_VALID(n) (1 << (n))
5879 5905
5906/* For UMS only (deprecated): */
5907#define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000)
5908#define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800)
5909#define _DPLL_A (dev_priv->info->display_mmio_offset + 0x6014)
5910#define _DPLL_B (dev_priv->info->display_mmio_offset + 0x6018)
5911#define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c)
5912#define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020)
5913
5880#endif /* _I915_REG_H_ */ 5914#endif /* _I915_REG_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-21 01:11:13 -0500