Merge tag 'drm-intel-next-2015-02-14' of git://anongit.freedesktop.org/drm-intel into drm-next

- use the atomic helpers for plane_upate/disable hooks (Matt Roper)
- refactor the initial plane config code (Damien)
- ppgtt prep patches for dynamic pagetable alloc (Ben Widawsky, reworked and
  rebased by a lot of other people)
- framebuffer modifier support from Tvrtko Ursulin, drm core code from Rob Clark
- piles of workaround patches for skl from Damien and Nick Hoath
- vGPU support for xengt on the client side (Yu Zhang)
- and the usual smaller things all over

* tag 'drm-intel-next-2015-02-14' of git://anongit.freedesktop.org/drm-intel: (88 commits)
  drm/i915: Update DRIVER_DATE to 20150214
  drm/i915: Remove references to previously removed UMS config option
  drm/i915/skl: Use a LRI for WaDisableDgMirrorFixInHalfSliceChicken5
  drm/i915/skl: Fix always true comparison in a revision id check
  drm/i915/skl: Implement WaEnableLbsSlaRetryTimerDecrement
  drm/i915/skl: Implement WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken
  drm/i915: Add process identifier to requests
  drm/i915/skl: Implement WaBarrierPerformanceFixDisable
  drm/i915/skl: Implement WaCcsTlbPrefetchDisable:skl
  drm/i915/skl: Implement WaDisableChickenBitTSGBarrierAckForFFSliceCS
  drm/i915/skl: Implement WaDisableHDCInvalidation
  drm/i915/skl: Implement WaDisableLSQCROPERFforOCL
  drm/i915/skl: Implement WaDisablePartialResolveInVc
  drm/i915/skl: Introduce a SKL specific init_workarounds()
  drm/i915/skl: Document that we implement WaRsClearFWBitsAtReset
  drm/i915/skl: Implement WaSetGAPSunitClckGateDisable
  drm/i915/skl: Make the init clock gating function skylake specific
  drm/i915/skl: Provide a gen9 specific init_render_ring()
  drm/i915/skl: Document the WM read latency W/A with its name
  drm/i915/skl: Also detect eDRAM on SKL
  ...

1 files changed, 46 insertions, 2 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 33b3d0a24071..1dc91de7d2e6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -140,6 +140,7 @@
 #define GEN8_RING_PDP_LDW(ring, n)      ((ring)->mmio_base+0x270 + (n) * 8)
 
 #define GAM_ECOCHK                      0x4090
+#define   BDW_DISABLE_HDC_INVALIDATION  (1<<25)
 #define   ECOCHK_SNB_BIT                (1<<10)
 #define   HSW_ECOCHK_ARB_PRIO_SOL       (1<<6)
 #define   ECOCHK_PPGTT_CACHE64B         (0x3<<3)
@@ -586,6 +587,19 @@ enum punit_power_well {
         PUNIT_POWER_WELL_NUM,
 };
 
+enum skl_disp_power_wells {
+        SKL_DISP_PW_MISC_IO,
+        SKL_DISP_PW_DDI_A_E,
+        SKL_DISP_PW_DDI_B,
+        SKL_DISP_PW_DDI_C,
+        SKL_DISP_PW_DDI_D,
+        SKL_DISP_PW_1 = 14,
+        SKL_DISP_PW_2,
+};
+
+#define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
+#define SKL_POWER_WELL_REQ(pw) (1 << (((pw) * 2) + 1))
+
 #define PUNIT_REG_PWRGT_CTRL                    0x60
 #define PUNIT_REG_PWRGT_STATUS                  0x61
 #define   PUNIT_PWRGT_MASK(power_well)          (3 << ((power_well) * 2))
@@ -1470,6 +1484,7 @@ enum punit_power_well {
 #define CACHE_MODE_1            0x7004 /* IVB+ */
 #define   PIXEL_SUBSPAN_COLLECT_OPT_DISABLE     (1<<6)
 #define   GEN8_4x4_STC_OPTIMIZATION_DISABLE     (1<<6)
+#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE    (1<<1)
 
 #define GEN6_BLITTER_ECOSKPD    0x221d0
 #define   GEN6_BLITTER_LOCK_SHIFT                       16
@@ -5221,15 +5236,22 @@ enum punit_power_well {
 #define HSW_NDE_RSTWRN_OPT      0x46408
 #define  RESET_PCH_HANDSHAKE_ENABLE     (1<<4)
 
+#define FF_SLICE_CS_CHICKEN2                    0x02e4
+#define  GEN9_TSG_BARRIER_ACK_DISABLE           (1<<8)
+
 /* GEN7 chicken */
 #define GEN7_COMMON_SLICE_CHICKEN1              0x7010
 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC      ((1<<10) | (1<<26))
+# define GEN9_RHWO_OPTIMIZATION_DISABLE         (1<<14)
 #define COMMON_SLICE_CHICKEN2                   0x7014
 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE   (1<<0)
 
 #define HIZ_CHICKEN                             0x7018
 # define CHV_HZ_8X8_MODE_IN_1X                  (1<<15)
 
+#define GEN9_SLICE_COMMON_ECO_CHICKEN0          0x7308
+#define  DISABLE_PIXEL_MASK_CAMMING             (1<<14)
+
 #define GEN7_L3SQCREG1                          0xB010
 #define  VLV_B0_WA_L3SQCREG1_VALUE              0x00D30000
 
@@ -5245,11 +5267,16 @@ enum punit_power_well {
 #define GEN7_L3SQCREG4                          0xb034
 #define  L3SQ_URB_READ_CAM_MATCH_DISABLE        (1<<27)
 
+#define GEN8_L3SQCREG4                          0xb118
+#define  GEN8_LQSC_RO_PERF_DIS                  (1<<27)
+
 /* GEN8 chicken */
 #define HDC_CHICKEN0                            0x7300
-#define  HDC_FORCE_NON_COHERENT                 (1<<4)
-#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED        (1<<11)
 #define  HDC_FENCE_DEST_SLM_DISABLE             (1<<14)
+#define  HDC_DONOT_FETCH_MEM_WHEN_MASKED        (1<<11)
+#define  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT    (1<<5)
+#define  HDC_FORCE_NON_COHERENT                 (1<<4)
+#define  HDC_BARRIER_PERFORMANCE_DISABLE        (1<<10)
 
 /* WaCatErrorRejectionIssue */
 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG          0x9030
@@ -5258,6 +5285,9 @@ enum punit_power_well {
 #define HSW_SCRATCH1                            0xb038
 #define  HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE   (1<<27)
 
+#define BDW_SCRATCH1                                    0xb11c
+#define  GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE      (1<<2)
+
 /* PCH */
 
 /* south display engine interrupt: IBX */
@@ -5980,6 +6010,7 @@ enum punit_power_well {
 #define  HSW_IDICR                              0x9008
 #define    IDIHASHMSK(x)                        (((x) & 0x3f) << 16)
 #define  HSW_EDRAM_PRESENT                      0x120010
+#define    EDRAM_ENABLED                        0x1
 
 #define GEN6_UCGCTL1                            0x9400
 # define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE              (1 << 16)
@@ -6003,6 +6034,7 @@ enum punit_power_well {
 #define GEN6_RSTCTL                             0x9420
 
 #define GEN8_UCGCTL6                            0x9430
+#define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE      (1<<24)
 #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE       (1<<14)
 
 #define GEN6_GFXPAUSE                           0xA000
@@ -6185,6 +6217,7 @@ enum punit_power_well {
 
 #define GEN9_HALF_SLICE_CHICKEN5        0xe188
 #define   GEN9_DG_MIRROR_FIX_ENABLE     (1<<5)
+#define   GEN9_CCS_TLB_PREFETCH_ENABLE  (1<<3)
 
 #define GEN8_ROW_CHICKEN                0xe4f0
 #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
@@ -6200,8 +6233,12 @@ enum punit_power_well {
 #define HALF_SLICE_CHICKEN3             0xe184
 #define   HSW_SAMPLE_C_PERFORMANCE      (1<<9)
 #define   GEN8_CENTROID_PIXEL_OPT_DIS   (1<<8)
+#define   GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC   (1<<5)
 #define   GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
 
+#define GEN9_HALF_SLICE_CHICKEN7        0xe194
+#define   GEN9_ENABLE_YV12_BUGFIX       (1<<4)
+
 /* Audio */
 #define G4X_AUD_VID_DID                 (dev_priv->info.display_mmio_offset + 0x62020)
 #define   INTEL_AUDIO_DEVCL             0x808629FB
@@ -6351,6 +6388,13 @@ enum punit_power_well {
 #define   HSW_PWR_WELL_FORCE_ON                 (1<<19)
 #define HSW_PWR_WELL_CTL6                       0x45414
 
+/* SKL Fuse Status */
+#define SKL_FUSE_STATUS                         0x42000
+#define  SKL_FUSE_DOWNLOAD_STATUS              (1<<31)
+#define  SKL_FUSE_PG0_DIST_STATUS              (1<<27)
+#define  SKL_FUSE_PG1_DIST_STATUS              (1<<26)
+#define  SKL_FUSE_PG2_DIST_STATUS              (1<<25)
+
 /* Per-pipe DDI Function Control */
 #define TRANS_DDI_FUNC_CTL_A            0x60400
 #define TRANS_DDI_FUNC_CTL_B            0x61400