diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2012-10-31 11:50:14 -0400 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-11-11 17:51:12 -0500 |
| commit | 57779d06367a915ee03e6cb918d7575f0a46e419 (patch) | |
| tree | 9546114f05253b6dd358d93b650afda9426a2e97 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | e7210c3c4f0d05e318b854bbd545fe335930c5cc (diff) | |
drm/i915: Fix display pixel format handling
Fix support for all RGB/BGR pixel formats (except the 16:16:16:16 float
format).
Fix intel_init_framebuffer() to match hardware and driver limitations:
* RGB332 is not supported at all
* CI8 is supported
* XRGB1555 & co. are supported on Gen3 and earlier
* XRGB210101010 & co. are supported from Gen4 onwards
* BGR formats are supported from Gen4 onwards
* YUV formats are supported from Gen5 onwards (driver limitation)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0514823e561b..d4520d5817c5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
| @@ -3009,12 +3009,19 @@ | |||
| 3009 | #define DISPPLANE_GAMMA_ENABLE (1<<30) | 3009 | #define DISPPLANE_GAMMA_ENABLE (1<<30) |
| 3010 | #define DISPPLANE_GAMMA_DISABLE 0 | 3010 | #define DISPPLANE_GAMMA_DISABLE 0 |
| 3011 | #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) | 3011 | #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) |
| 3012 | #define DISPPLANE_YUV422 (0x0<<26) | ||
| 3012 | #define DISPPLANE_8BPP (0x2<<26) | 3013 | #define DISPPLANE_8BPP (0x2<<26) |
| 3013 | #define DISPPLANE_15_16BPP (0x4<<26) | 3014 | #define DISPPLANE_BGRA555 (0x3<<26) |
| 3014 | #define DISPPLANE_16BPP (0x5<<26) | 3015 | #define DISPPLANE_BGRX555 (0x4<<26) |
| 3015 | #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) | 3016 | #define DISPPLANE_BGRX565 (0x5<<26) |
| 3016 | #define DISPPLANE_32BPP (0x7<<26) | 3017 | #define DISPPLANE_BGRX888 (0x6<<26) |
| 3017 | #define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) | 3018 | #define DISPPLANE_BGRA888 (0x7<<26) |
| 3019 | #define DISPPLANE_RGBX101010 (0x8<<26) | ||
| 3020 | #define DISPPLANE_RGBA101010 (0x9<<26) | ||
| 3021 | #define DISPPLANE_BGRX101010 (0xa<<26) | ||
| 3022 | #define DISPPLANE_RGBX161616 (0xc<<26) | ||
| 3023 | #define DISPPLANE_RGBX888 (0xe<<26) | ||
| 3024 | #define DISPPLANE_RGBA888 (0xf<<26) | ||
| 3018 | #define DISPPLANE_STEREO_ENABLE (1<<25) | 3025 | #define DISPPLANE_STEREO_ENABLE (1<<25) |
| 3019 | #define DISPPLANE_STEREO_DISABLE 0 | 3026 | #define DISPPLANE_STEREO_DISABLE 0 |
| 3020 | #define DISPPLANE_SEL_PIPE_SHIFT 24 | 3027 | #define DISPPLANE_SEL_PIPE_SHIFT 24 |