drm/i915: Enable/Disable PSR

Adding Enable and Disable PSR functionalities. This includes setting the
PSR configuration over AUX, sending SDP VSC DIP over the eDP PIPE config,
enabling PSR in the sink via DPCD register and finally enabling PSR on
the host.

This patch is based on initial PSR code by Sateesh Kavuri and Kumar Shobhit
but in a different implementation.

v2: * moved functions around and changed its names.
    * removed VSC DIP unset from disable.
    * remove FBC wa.
    * don't mask LSPS anymore.
    * incorporate new crtc usage after a rebase.
v3: Make a clear separation between Sink (Panel) and Source (HW) enabling.
v4: Fix identation and other style issues raised by checkpatch (by Paulo).
v5: Changes according to Paulo's review:
    static on write_vsc;
    avoid using dp_to_dev when already calling dp_to_dig_port;
    remove unecessary TP default time setting;
    remove unecessary interrupts disabling;
    remove unecessary wait_for_vblank when disabling psr;
v6: remove unecessary wait_for_vblank when writing vsc;
v7: adding setup once function to avoid unnecessarily write to vsc
    and set debug_ctl every time we enable or disable psr.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Credits-by: Sateesh Kavuri <sateesh.kavuri@intel.com>
Credits-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com>
[danvet: Apply Paulo's suggestion for unconditionally clearing the
control register when writing the DIP.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 42 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5e58a44c5fe3..56cb79d4a980 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1779,6 +1779,47 @@
 #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
 #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
 
+/* HSW eDP PSR registers */
+#define EDP_PSR_CTL                             0x64800
+#define   EDP_PSR_ENABLE                        (1<<31)
+#define   EDP_PSR_LINK_DISABLE                  (0<<27)
+#define   EDP_PSR_LINK_STANDBY                  (1<<27)
+#define   EDP_PSR_MIN_LINK_ENTRY_TIME_MASK      (3<<25)
+#define   EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES   (0<<25)
+#define   EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES   (1<<25)
+#define   EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES   (2<<25)
+#define   EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES   (3<<25)
+#define   EDP_PSR_MAX_SLEEP_TIME_SHIFT          20
+#define   EDP_PSR_SKIP_AUX_EXIT                 (1<<12)
+#define   EDP_PSR_TP1_TP2_SEL                   (0<<11)
+#define   EDP_PSR_TP1_TP3_SEL                   (1<<11)
+#define   EDP_PSR_TP2_TP3_TIME_500us            (0<<8)
+#define   EDP_PSR_TP2_TP3_TIME_100us            (1<<8)
+#define   EDP_PSR_TP2_TP3_TIME_2500us           (2<<8)
+#define   EDP_PSR_TP2_TP3_TIME_0us              (3<<8)
+#define   EDP_PSR_TP1_TIME_500us                (0<<4)
+#define   EDP_PSR_TP1_TIME_100us                (1<<4)
+#define   EDP_PSR_TP1_TIME_2500us               (2<<4)
+#define   EDP_PSR_TP1_TIME_0us                  (3<<4)
+#define   EDP_PSR_IDLE_FRAME_SHIFT              0
+
+#define EDP_PSR_AUX_CTL                 0x64810
+#define EDP_PSR_AUX_DATA1               0x64814
+#define   EDP_PSR_DPCD_COMMAND          0x80060000
+#define EDP_PSR_AUX_DATA2               0x64818
+#define   EDP_PSR_DPCD_NORMAL_OPERATION (1<<24)
+#define EDP_PSR_AUX_DATA3               0x6481c
+#define EDP_PSR_AUX_DATA4               0x64820
+#define EDP_PSR_AUX_DATA5               0x64824
+
+#define EDP_PSR_STATUS_CTL                      0x64840
+#define   EDP_PSR_STATUS_STATE_MASK             (7<<29)
+
+#define EDP_PSR_DEBUG_CTL               0x64860
+#define   EDP_PSR_DEBUG_MASK_LPSP       (1<<27)
+#define   EDP_PSR_DEBUG_MASK_MEMUP      (1<<26)
+#define   EDP_PSR_DEBUG_MASK_HPD        (1<<25)
+
 /* VGA port control */
 #define ADPA                    0x61100
 #define PCH_ADPA                0xe1100
@@ -2048,6 +2089,7 @@
  * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
  * of the infoframe structure specified by CEA-861. */
 #define   VIDEO_DIP_DATA_SIZE   32
+#define   VIDEO_DIP_VSC_DATA_SIZE       36
 #define VIDEO_DIP_CTL           0x61170
 /* Pre HSW: */
 #define   VIDEO_DIP_ENABLE              (1 << 31)